Enabling shallow trench isolation for 0.1 μm technologies and beyond

Chang, C.P.; Shive, S.F.; Kuehne, S.C.; Ma, Y.; Vuong, H.-H.; Baumann, F.H.; Bude, M.; Lloyd, Emily; Pai, C.S.; Abdelgadir, M.A.; Dail, R.; Liu, C.T.; Cheung, Kin P.; Colonell, Jennifer; Lai, Wang; Miner, J.F.; Vaidya, H.; Liu, R.C.; Clemens, J.T.

doi:10.1109/vlsit.1999.799393

Cited by 6 publications

(1 citation statement)

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“…Silicon corner rounding is commonly achieved via high temperature oxidation of the trench sidewalls [2]. Preventing gate wrap-around is more problematic since significant oxide recess is likely to originate from all (isotropic) HF oxide etch steps that are carried out between the post-planarisation nitride etch and gate stack deposition.…”

Section: Introductionmentioning

confidence: 99%

Controlling STI-related Parasitic Conduction in 90 nm CMOS and Below

Augendre

Rooyackers²,

Shamiryan³

et al. 2002

32nd European Solid-State Device Research Conference

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In parallel to its continuous scaling, shallow trench isolation (STI) requires thorough optimisation with respect to its impact on device performance. In particular, the conduction occurring at the isolation edge of the device needs to be limited. Among the factors that influence the related control of threshold voltage and subthreshold current, this paper evaluates the impact of process parameters such as transistor architecture, trench profile (conventional or T-shape) and, for the first time, sacrificial oxidation strategy.It is first proven that conventional STI architecture can provide the same gate oxide integrity and control of lateral conduction as T-shape STI. Second, it is shown that transistor scaling improves immunity to narrow channel effects. This is illustrated with an optimised conventional STI module showing hump-free operation and threshold voltage variation of 40 mV down to 0.11 µm wide nMOS transistors, making the approach suitable at least down to the 90 nm technology node.

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Section: Introductionmentioning

confidence: 99%