ENDEAVOUR to understand EUV buried defect printability

Seki, Kazunori; Isogawa, Takeshi; Kagawa, M.; Akima, Shinji; Kodera, Yutaka; Badger, Karen; Qi, Zhengqing John; Lawliss, Mark; Rankin, Jed; Bonam, Ravi

doi:10.1117/12.2197763

Cited by 4 publications

(3 citation statements)

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“…12,33,34 To identify all potential defects buried in the multilayer stack, actinic blank inspection (ABI) at 13.5 nm is required. 13 Despite the potential impact on the conclusions made in this work, actinic inspection tools under development are not considered as it is uncertain when ABI and actinic pattern mask inspection tools will reach HVM availability.…”

Section: Viability Of Defect-free Masks For 7 Nm Nodementioning

confidence: 99%

“…5 Recent efforts have limited blank defects greater than 54 nm in size, 6 however much experimental work have shown that smaller defects also requires elimination. [7][8][9][10][11][12][13] The lack in highvolume availability of pristine defect-free blanks as well as the absence of a robust mask repair technique 14,15 mandates defect mitigation through pattern shift for intersecting HVM. By using known defect locations on a blank, the mask design can be intentionally shifted to avoid patterning a desired reflective region directly over a defect.…”

Section: Introductionmentioning

confidence: 99%

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Defect avoidance for EUV photomask readiness at the 7 nm node

Rankin

Narita

et al. 2016

SPIE Proceedings

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Several challenges hinder extreme ultraviolet lithography (EUVL) photomask fabrication and its readiness for high volume manufacturing (HVM). The lack in availability of pristine defect-free blanks as well as the absence of a robust mask repair technique mandates defect mitigation through pattern shift for the production of defect-free photomasks. The work presented here provides a comprehensive look at pattern shift implementation to intersect EUV HVM for the 7 nm technology node. An empirical error budget to compensate for measurement variability and errors, based on the latest HVM inspection and write tool capabilities, is first established and then experimentally verified. The validated error budget is applied to 20 representative EUV blanks and pattern shift is performed on fully functional 7 nm node chip designs. The probability of defect-free masks is explored for various layers, including metal, contact, and gate cut layers. From these results, an assessment is made on the current viability of defect-free EUV masks and what is required to construct a complete defect-free EUV mask set.

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Section: Viability Of Defect-free Masks For 7 Nm Nodementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Defect avoidance for EUV photomask readiness at the 7 nm node

Rankin

Narita

et al. 2016

SPIE Proceedings

Self Cite

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show abstract

“…This reflective design introduces a new class of defects not seen in previous mask technologies. [4][5][6][7][8][9] As such, EUV mask defectivity remains a persistent obstacle that must be addressed in order to enable EUVL high-volume manufacturing (HVM).…”

Section: Introductionmentioning

confidence: 99%