Energy and bandwidth aware mapping of IPs onto regular NoC architectures using Multi-Objective Genetic Algorithms

Bhardwaj, Kshitij; Jena, Rabindra Kumar

doi:10.1109/socc.2009.5335684

Cited by 20 publications

(16 citation statements)

References 5 publications

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“…A multi-objective Genetic Algorithm (MOGA) based application mapping technique has been proposed in [28], where one-one as well as many-many mapping between switches and tiles have been taken into consideration to minimize energy consumption and required link bandwidth. In [29], CGMAP, a genetic algorithm based application mapping technique has been proposed that uses the chaotic mapping operator instead of the random processes in GA. GAMR [30], a genetic algorithm based mapping and routing approach addresses a two phase mapping of IP cores onto NoC architecture and generates a deterministic dead-lock free minimal routing path for each communication to minimize the total communication energy and maximum link bandwidth of the NoC architecture.…”

Section: Literature Surveymentioning

confidence: 99%

Thermal Uniformity-Aware Application Mapping for Network-on-Chip Design

Sahu¹,

Manna²,

Shah³

et al. 2014

IJCA

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Ensuring thermal-uniformity in an integrated circuit chip is very essential for its correct operation. Thus, in the Networkon-Chip (NoC) based system design as well, it is essential to attach cores of the application core graph to the routers in the topology graph so that thermal uniformity across the chip is maintained. However, the performance of the application should not be sacrificed to a great extent. Also, the CPU time needed to explore the overall search-space is quite high. This paper presents a tool to the designers to explore the searchspace in a controlled fashion. The designer can specify the communication cost degradation that can be tolerated and the amount of effort put in to identify the potential solutions. All non-dominated solutions (in terms of communication cost and temperature variance) are reported from which the designer can choose the appropriate one for implementation.

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Section: Literature Surveymentioning

confidence: 99%

Thermal Uniformity-Aware Application Mapping for Network-on-Chip Design

Sahu¹,

Manna²,

Shah³

et al. 2014

IJCA

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“…This algorithm has been implemented and evaluated on three randomly generated benchmarks of a varied number of IP cores [15] and a well known application, namely Video Object Plane Decoder (VOPD) with 16 IP cores [11], [16]. And then, we compare the simulation results among PHA and some previous mapping algorithms such as MOGA [15] and TGA [17].…”

Section: Introductionmentioning

confidence: 99%

“…And then, we compare the simulation results among PHA and some previous mapping algorithms such as MOGA [15] and TGA [17]. The optimization objectives of MOGA are energy consumption and maximal link bandwidth, and the optimization objective of TGA is latency.…”

Section: Introductionmentioning

confidence: 99%

Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip

Sun

Lin

Jin

et al. 2011

IEICE Trans. Inf. & Syst.

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SUMMARYNetwork on Chip (NoC) is proposed as a new intra-chip communication infrastructure. In current NoC design, one related problem is mapping IP cores onto NoC architectures. In this paper, we propose a performance-aware hybrid algorithm (PHA) for mesh-based NoC to optimize performance indexes such as latency, energy consumption and maximal link bandwidth. The PHA is a hybrid algorithm, which integrates the advantages of Greedy Algorithm, Genetic Algorithm and Simulated Annealing Algorithm. In the PHA, there are three features. First, it generates a fine initial population efficiently in a greedy swap way. Second, effective global parallel search is implemented by genetic operations such as crossover and mutation, which are implemented with adaptive probabilities according to the diversity of population. Third, probabilistic acceptance of a worse solution using simulated annealing method greatly improves the performance of local search. Compared with several previous mapping algorithms such as MOGA and TGA, simulation results show that our algorithm enhances the performance by 30.7%, 23.1% and 25.2% in energy consumption, latency and maximal link bandwidth respectively. Moreover, simulation results demonstrate that our PHA approach has the highest convergence speed among the three algorithms. These results show that our proposed mapping algorithm is more effective and efficient.

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mentioning

confidence: 99%

“…In second step, the IPs are mapped to tiles of NoC taking the actual edge delay based on the network traffic model, and the total system delay is minimized. A multi-objective Genetic Algorithm (MOGA) based application mapping technique has been proposed in [27], where one-one as well as many-many mapping between switches and tiles have been taken into consideration to minimize energy consumption and required link bandwidth. In [28], CGMAP, a genetic algorithm based application mapping technique has been proposed that uses the chaotic mapping operator instead of the random processes in GA. GAMR [29], a genetic algorithm based mapping and routing approach addresses a two phase mapping of IP cores onto NoC architecture and generates a deterministic dead-lock free minimal routing path for each communication to minimize the total communication energy and maximum link bandwidth of the NoC architecture.…”

mentioning

confidence: 99%

Application Mapping onto Butterfly-Fat-Tree based Network-on-Chip using Discrete Particle Swarm Optimization

Sahu¹,

Manna²,

Chattopadhyay³

2015

IJCA

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This paper addresses the problem of application mapping onto Butterfly-Fat-Tree (BFT) based Network-on-Chip design. It proposes a new mapping technique based on discrete Particle Swarm Optimization (PSO) to map the cores of the core graph to the routers. The basic PSO has been augmented by running multiple PSO and deterministically generating a part of the initial population for PSO. The mapping results have been compared with well-known techniques reported in the literature for a number of benchmark applications. The reported strategy produces results superior to those obtained via existing approaches within a reasonable CPU time. KeywordsApplication mapping, Network-on-Chip, System-on-Chip, Butterfly-Fat-Tree, Discrete Particle Swarm Optimization INTRODUCTIONNetwork-on-Chip (NoC) has evolved as a viable strategy to implement Intellectual Property (IP) core based System-onChip (SoC) designs. It solves the traditional problems of bandwidth limitations of bus-based SoC design by providing an on-chip network fabric consisting of routers connected in a certain topology. Conventional data signal exchanges are replaced by message passing between the cores through the router fabric [1]- [4]. A major challenge in NoC based system design is to associate the IP cores implementing tasks of an application with routers. This is commonly known as the process of application mapping. This has got a very significant role to play in performance of the overall system as it directly influences the communication time, the required link bandwidth, the admissible delay of the router, and energy consumption of the whole NoC [5], [6]. Furthermore, these requirements vary from one application domain to another. For example, while multimedia applications require high bandwidth, real time systems require guaranteed delay, and portable devices require low power consumption. Most of the application mapping algorithms reported in the literature assumes a mesh-connected router fabric for the NoC. In [6]- [10], authors have proposed many topologies for NoC. Butterfly-Fat-Tree (BFT) enjoys several advantages over other topologies [7], [10]. The BFT topology can be easily implemented inside chips. It has the advantage of having small diameter as well as symmetric structure. There are various versions of the networks connected in the tree like architecture and most of them have recursive structures. The wire routing is also simpler. In chip design, for same number of cores, the area occupied by BFT is less than the mesh topology. These characteristics make BFT a popular scheme for interconnecting IPs [7], [10]. In [7] stage. This ensures faster convergence and improved quality of solution for the successive stages.3. For any stage of PSO, the initial population generation is not fully random. A good number of particles have been created using a heuristic. This has enabled our PSO to explore the promising regions of search space much better.4. The communication cost metric values of the mapping solutions of our approach have been compared ...

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Energy and bandwidth aware mapping of IPs onto regular NoC architectures using Multi-Objective Genetic Algorithms

Cited by 20 publications

References 5 publications

Thermal Uniformity-Aware Application Mapping for Network-on-Chip Design

Thermal Uniformity-Aware Application Mapping for Network-on-Chip Design

Performance-Aware Hybrid Algorithm for Mapping IPs onto Mesh-Based Network on Chip

Application Mapping onto Butterfly-Fat-Tree based Network-on-Chip using Discrete Particle Swarm Optimization

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