Energy-aware mapping for tile-based NoC architectures under performance constraints

Hu, Junjie; Mărculescu, Radu

doi:10.1145/1119772.1119818

Cited by 459 publications

(340 citation statements)

References 7 publications

Supporting

Mentioning

336

Contrasting

Unclassified

Order By: Relevance

“…This is considerably higher than those of the real application studied in [5]. We also considered that at the design time, the number of IP cores of an application is equal to the number of available tiles on the mesh platform.…”

Section: Resultsmentioning

confidence: 99%

“…Regarding the application mapping optimization, the mapping and routing path allocation problem for tile based architectures have been addressed in [3,4,5,6,7,8]. In [5], an energy aware mapping and scheduling approach has been addressed.…”

Section: Related Workmentioning

confidence: 99%

“…In [5], an energy aware mapping and scheduling approach has been addressed. It uses a heuristic approach for core mapping which tends to run much faster than Genetic Algorithm (GA) based approaches.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip

Mehran

Khademzadeh

Saeidi

2008

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:In this paper, a heuristic Dynamic Spiral Mapping (DSM) algorithm for 2-D mesh topologies is proposed. Based on the DSM we have presented two different approaches: the Full Dynamic Spiral Mapping (FDSM) and the Partial Dynamic Spiral Mapping (PDSM). To compare the efficacy of the algorithm, the reconfiguration time of the FDSM and PDSM are compared. The experimental results of almost 100 simple and complex scenarios with synthetic traffic profiles reveal that in 82% of simulation cases, the PDSM has less reconfiguration time comparing to the FDSM.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip

Mehran

Khademzadeh

Saeidi

2008

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…The application task graphs of MPEG4, PIP, MWD are taken from [12]. The task graphs of H.263 encoding, MP3 encoding, and MMS are taken from [13]. The task graphs of 802.11 MAC, TCP checksum, VOPD are taken from [14], [15], [16], respectively.…”

Section: Implementation and Resultsmentioning

confidence: 99%

Customizing Reconfigurable On-Chip Crossbar Scheduler

Hur

Stefanov

Wong

et al. 2007

2007 IEEE International Conf. On Application-Specific Systems, Architectures and Processors (ASAP)

View full text Add to dashboard Cite

show abstract

“…Several optimization methods have been proposed to reduce energy consumption through application specific customizations. These include: customized router buffer sizing [15]; custom topology generation [25]; adaptive routing [16]; and mapping processing elements to tiles [14,21].…”

Section: Introductionmentioning

confidence: 99%

Nocee : energy macro-model extraction methodology for network on chip routers

Chan¹,

Parameswaran²

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

View full text Add to dashboard Cite

In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the relationship between events occurring in the NoC and energy consumption. The resulting models are cycle accurate and can be applied to different technology libraries. We verify the individual router estimation models with many different synthetically generated traffic patterns and data inputs. Characterization of a small library takes about two hours. The mean absolute energy estimation error of the resultant models is 5% (10% max) against a complete gate level simulation. We also apply this method to a number of complete NoCs with inputs extracted from synthetic application traces and compare our estimated results to the gate level power simulations (mean absolute error is 5%). Our estimation methodology has been integrated with commercial logic synthesis flow and power estimation tools (Synopsys Design Compiler and PrimePower), allowing application across different designs. The extracted models show the different trends across various parameterizations of Network on Chip routers and have been integrated into an architecture exploration framework.

show abstract

Energy-aware mapping for tile-based NoC architectures under performance constraints

Cited by 459 publications

References 7 publications

DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip

DSM: A Heuristic Dynamic Spiral Mapping algorithm for network on chip

Customizing Reconfigurable On-Chip Crossbar Scheduler

Nocee : energy macro-model extraction methodology for network on chip routers

Contact Info

Product

Resources

About