Energy efficiency in real-time systems: A brief overview

Stangaciu, Cristina S.; Micea, Mihai V.; Creţu, Vladimir

doi:10.1109/saci.2013.6608981

Cited by 18 publications

(9 citation statements)

References 30 publications

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“…Power management methods can be of static or dynamic nature. Dynamic Power Management (DPM) (also called Power Mode Management: PMM) [17] reduces energy consumption by the utilisation of different low-power modes (e.g., idle, sleep, stand-by) which are realised through combination of LPT supported by the underlying hardware. In every mode, different energy budgets and response times are needed.…”

Section: A Overview Of Power Management Techniquesmentioning

confidence: 99%

A Hypervisor Architecture for Low-Power Real-Time Embedded Systems

Poggi¹,

Onaindia²,

Azkarate-askatsua³

et al. 2018

2018 21st Euromicro Conference on Digital System Design (DSD)

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This paper presents a hypervisor architecture tailored to low-power real-time applications. This architecture extends the capability of a hypervisor by providing power management techniques and power monitoring services. An implementation based on an existing hypervisor XtratuM that runs over the ARM of a Zynq-7000 SoC device is proposed as a proof of concept. Measurement results show that the extended hypervisor can obtain information on the power consumption and reduce it.

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Section: A Overview Of Power Management Techniquesmentioning

confidence: 99%

A Hypervisor Architecture for Low-Power Real-Time Embedded Systems

Poggi¹,

Onaindia²,

Azkarate-askatsua³

et al. 2018

2018 21st Euromicro Conference on Digital System Design (DSD)

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“…Using Dynamic Power Management (DPM) (also called Power Mode Management: PMM) [11] based on low power modes (e.g., idle, sleep, stand-by) supported by the underlying hardware can bring much in terms of energy saving. In every mode, different energy budgets and response times are needed.…”

Section: A Energy Minimization Techniquesmentioning

confidence: 99%

“…DVFS, clock and power gating techniques can be used for this purpose and can be extended on the management of devices. In the recent years, many techniques, which decide an on-line or offline schedule to guarantee the task deadlines while minimizing the CPU energy consumption, have proliferated in journals and conference papers ( [7], [11], [37]). Considering the transition time between different power consumption modes is critical.…”

Section: State Of the Art Low-power Technologiesmentioning

confidence: 99%

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Fakih

Lenz

Azkarate-Askasua

et al. 2017

Microprocessors and Microsystems

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With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER 1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

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“…After the successful application of DVFS technique to the unicore processors, it has also been carried out on some of the multi-core processors with or without splitted task [14], [15], [16], [17]. When using multi-core processors DVFS can be applied asi) POST-DVFS -Here, a schedule is first made with the splitted task to evaluate the schedulability and energy consumption.…”

Section: Related Workmentioning

confidence: 99%

Energy Efficient Scheduling Algorithm for Applying Dynamic Voltage and Frequency Scaling to Mixed Task Set

Mehariya¹,

Songara²,

Mitra³

et al. 2014

IJCA

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Power consumption is one of the most important factors that affect the designing of battery operated real-time system or an embedded system. Various strategies have been made to improve the power dissipation. Dynamic voltage and frequency scaling (DVFS), is one of the most popular technique for reducing power dissipation and a well researched area. This paper presents DVFSMTS, Dynamic Voltage and Frequency Scaling for Mixed Task Set, which gives the working of an Earliest Deadline First (EDF), based priority exchange server. Experimental results show that DVFSMTS reduces power dissipation without compromising on the deadlines of the periodic task. The results of DVFSMTS are compared with a non-DVFS EDF based priority exchange server and an approximate 50% reduction in energy is obtained.

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Energy efficiency in real-time systems: A brief overview

Cited by 18 publications

References 30 publications

A Hypervisor Architecture for Low-Power Real-Time Embedded Systems

A Hypervisor Architecture for Low-Power Real-Time Embedded Systems

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Energy Efficient Scheduling Algorithm for Applying Dynamic Voltage and Frequency Scaling to Mixed Task Set

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