Energy efficient current-mode signaling scheme

Dave, Marshnil; Jain, Mahavir; Satkuri, Rajkumar; Baghini, Maryam Shojaei; Sharma, Dinesh K.

doi:10.1109/asscc.2010.5716571

Cited by 5 publications

(1 citation statement)

References 6 publications

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“…On the other hand, the systems we put on integrated circuits increase at a rate higher than the rate at which device sizes shrink. Thus, the global interconnect wire lengths on a chip show an increasing trend which leads to a sharp increasing in delay [2]. Consequently, the performance of global interconnects has become the bottleneck of the performance in modern VLSI design using scaled down technologies [3].…”

Section: Introductionmentioning

confidence: 99%

Robust current-mode on-chip interconnect signaling scheme in deep submicron

Wang

2013

2013 IEEE 10th International Conference on ASIC

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In this paper, we propose a novel process-variation robust current-mode signaling scheme for on-chip interconnects. By using special bias generation circuits in the driver, the current-mode signaling system is robust in the presence of process induced parameter variations and uncertainties. Different process corners and Monte Carlo simulation analyses are carried out using Hspice in Chartered Semiconductor 0.18 micrometer process. The process corner simulation analyses show that the average power and system delay don't change much in different process corner, especially in typical, FS and SF corner. Monte Carlo analyses show that the average delay and power of the interconnect signaling system are normally distributed for a 10mm wire in 180 nm process technology.

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Section: Introductionmentioning

confidence: 99%

Robust current-mode on-chip interconnect signaling scheme in deep submicron

Wang

2013

2013 IEEE 10th International Conference on ASIC

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Close form delay model for on chip signalling with resistive load termination using: Current mode technique

Jadav

Vashishth

Chandel

2014

2014 9th International Conference on Industrial and Information Systems (ICIIS)

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A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

Kancharapu

Dave

Masimukkula

et al. 2011

2011 IEEE Computer Society Annual Symposium on VLSI

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A current-mode clock distribution network (CM-CDN) for low-power low-skew on-chip clock distribution is presented in this paper. A novel low-power current-mode receiver circuit with common-mode correction for the CM-CDN is also presented. The CM-CDN and associated receiver circuit are designed and optimized in 90nm CMOS process with 1V supply voltage. The performance of the proposed CM-CDN is analyzed and simulated under parameter variations using corner analysis as well as Monte Carlo model files provided by the foundry. It is shown that the worst case skew of a 1-Level H-Tree CM-CDN is 21ps considering on-chip process variation whereas skew of an optimized voltage-mode CDN (VM-CDN) in the same process is 33ps. Power consumption of the proposed CM-CDN operating at 4GHz is 6.28mW which is 57% less as compared to the voltage-mode CDN. Also for the same input impedance of 200Ω, the proposed receiver consumes a power of 521.4μW which is 35% less than that of state of the art current-mode receiver.

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Energy efficient current-mode signaling scheme

Cited by 5 publications

References 6 publications

Robust current-mode on-chip interconnect signaling scheme in deep submicron

Robust current-mode on-chip interconnect signaling scheme in deep submicron

Close form delay model for on chip signalling with resistive load termination using: Current mode technique

A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

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