A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

Kancharapu, Naveen Kumar; Dave, Marshnil; Masimukkula, Veerraju; Baghini, Maryam Shojaei; Sharma, Dinesh K.

doi:10.1109/isvlsi.2011.80

Cited by 7 publications

(3 citation statements)

References 10 publications

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“…The representative CM scheme in Figure 1 uses a CMOS inverter as the Tx while the Rx is based on a transimpedance amp [7]. This scheme provides delay improvement over VM schemes, but the Rx voltage swings around a common-mode voltage (V CM ) and any V CM shift would cause a large CDN skew [8]. Previous CM schemes used an expensive transimpedance amp Rx which could result in significant skew due to V CM shift if applied to CDNs [7].…”

Section: Overview Of Existing CM Signaling Schemesmentioning

confidence: 99%

Current-mode clock distribution

Islam¹,

Guthaus²

2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high-performance current-mode pulsed flipflop (CMPFF) using a representative 45nm CMOS technology. When the CMPFF is combined with a CM transmitter, the first CM clock distribution network exhibits 45.2% lower average power compared to traditional voltage mode clocks.

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Section: Overview Of Existing CM Signaling Schemesmentioning

confidence: 99%

Current-mode clock distribution

Islam¹,

Guthaus²

2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Current-mode (CM) signals are more robust to variability and consume less power compared to the counterpart voltagemode (VM) signals [5]- [9], [14]. However, most CM signaling is restricted to off-chip one-to-one signal transmission [6], [8].…”

Section: Introductionmentioning

confidence: 99%

“…However, most CM signaling is restricted to off-chip one-to-one signal transmission [6], [8]. Only in recent years have researchers started using CM signaling in CDNs to achieve higher reliability and lower power compared to traditional buffered VM clocking [5], [7], [10]- [12]. While most of these works addressed clock reliability issues, considering process variation, transistor mismatch, supply-voltage fluctuation, and crosstalk induced skew, they focused mainly on skew and did not consider clock jitter.…”

Section: Introductionmentioning

confidence: 99%

HCDN: Hybrid-Mode Clock Distribution Networks

Islam

Guthaus

2019

IEEE Trans. Circuits Syst. I

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We propose a new hybrid clock distribution scheme that uses global current-mode (CM) and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking is bufferless and relies on current rather than voltage, which reduces the jitter. The local VM network improves compatibility with traditional CMOS logic. The hybrid clock distribution network exhibits 29% lower average power and 54% lower jitter-induced skew in a symmetric network compared to traditional VM clocks. To use hybrid clocking efficiently, we present a methodology to identify the optimal cluster size and the number of required receiver circuits, which we demonstrate using the ISPD 2009, ISPD 2010, and ISCAS89 testbench networks. At 1-2GHz clock frequency, the proposed methodology uses up to 45% and 42% lower power compared to a synthesized buffered VM scheme using ISPD 2009 and ISPD 2010 testbenches, respectively. In addition, the proposed hybrid clocking scheme saves up to 50% and 59% of power compared to a buffered scheme using the ISCAS89 benchmark circuit at 1GHz and 2GHz clock frequency, respectively.

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