Energy-efficient data retention in D flip-flops using STT-MTJ

Abstract

Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

A low power high speed single phase clock level restoring 16T master-slave flip-flop

“…TCFF consists of 21 but not suitable for high-frequency operation. LRFF has 19 transistors only but has more power loss (Jyothula, 2018; Monga et al , 2020). The recently reported 18TSPC (in Figure 6) master-slave flip-flop, which have higher clock to Q delay and it has a problem in standby MODE also.…”

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

“…In the prior art there are two approaches to achieve a low leakage flip-flop (FF) with data retention capability 1) nonvolatile data retention FF (NV-FF) [1], [2], [3], [4], [5], [6], [7], [8], [9], [10] and 2) CMOS FF with a balloon latch (DR-FF). The NV-FF allows zero power consumption to maintain the data during the sleep mode, whereas the DR-FF requires an always-on circuity to preserve the data [11], [12], [13], [14], [15], [16].…”

“…Digital Object Identifier 10.1109/TCSII.2023.3238961 have limited endurance. For example, RRAM and MTJ NV-FFs have a maximum write endurance of 10 9 and 10 12 cycles, respectively [8]. 3) NV-FFs require a high transition mode supply voltage as well (> 1 V), which makes them difficult to integrate in systems [17].…”