Energy-efficient implementation of a wideband transceiver system with per-band equalisation and synchronisation

Abstract

For emission in the TV white space spectrum, the regulators are imposing strict spectral masks, which can be fulfilled using a DFT-modulated filter-bank multi-carrier system to extract one or several TVWS channels in the 470-790MHz range. Such a system reduces the channel dispersion, but even with nearperfectly reconstructing filter banks, an equaliser is required to at least perform some form of timing synchronisation. In this work, we propose a per-band equalisation and synchronisation approach, performed by a constant modulus (CM) algorithm running concurrently with a decision-directed adaptation process for faster convergence and reduced phase ambiguity. We compare symbol-and fractionally-spaced versions, and investigate their fixed-point implementation on a field programmable gate array. We elaborate on advantages that this fractionally spaced concurrent system offers over a symbol-spaced equaliser and compare it to equalisers that are updated purely by a CM algorithm.

Multi-Radio Access Network Assignment Using Dynamic Programming

“…The algorithm is effective in reducing the power consumption of the GHz PTMP radio, providing up to 3% energy saving against a maximum reach policy. Together with efforts towards a low-power basestation implementation [9], [28], [29], this algorithm can permit a downsizing of the power supply systems (harvesters and batteries), thus reducing the cost of the base station, as demonstrated in simulation by reducing the harvesting capacity of the BS to 25%. Furthermore the algorithm can provide a better balance between the number of users assigned to each of the networks, and is therefore capable of enhancing the quality of service.…”

FPGA Implementation of a TVWS Up- and Downconverter Using Non-Power-of-Two FFT Modulated Filter Banks

“…As discussed in previous work [14], for signal processing applications the most critical resources on a FPGA are the MAC units, contained in the DSP48E1 modules of Xilinx's FPGAs. To that respect, the serialised versions of the FFT as proved more area-efficient for every implementation, allowing the larger transforms, such as the the 56-and 64-point FFT to fit on the FPGA, when a parallel version would use more resources than available.…”

“…The reduced use of DSP48E1 however comes to the price of an increased number of RAM blocks necessary, which are most likely mapped to serialto-parallel and parallel-to-serial conversions. This trade-off is however very advantageous as it make use of an otherwise unused resource, allowing to reassign the DSP48E1 block for other tasks, such as equalisation and/or synchronisation [14]- [16]. The most area-efficient version of the system is the FBMC system implementing the 40-point serial version of the FFT, showing reduced block use against the 64-point FFT version in all type of resources.…”