FPGA Implementation of a TVWS Up- and Downconverter Using Non-Power-of-Two FFT Modulated Filter Banks

Anis, Vianney; Guo, Jincheng; Weiss, Stephan; Crockett, Louise H.

doi:10.23919/eusipco.2019.8902588

Cited by 2 publications

(2 citation statements)

References 16 publications

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“…The algorithm is effective in reducing the power consumption of the GHz PTMP radio, providing up to 3% energy saving against a maximum reach policy. Together with efforts towards a low-power basestation implementation [9], [28], [29], this algorithm can permit a downsizing of the power supply systems (harvesters and batteries), thus reducing the cost of the base station, as demonstrated in simulation by reducing the harvesting capacity of the BS to 25%. Furthermore the algorithm can provide a better balance between the number of users assigned to each of the networks, and is therefore capable of enhancing the quality of service.…”

Section: Resultsmentioning

confidence: 99%

Multi-Radio Access Network Assignment Using Dynamic Programming

Anis

Weiss

2019

2019 International Conference on Software, Telecommunications and Computer Networks (SoftCOM)

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This paper addresses the formulation of an optimisation problem that assigns a user to a multi-network base station for rural broadband access. The base station in this work is a fully off-grid-powered by renewable energy-system with a wireless backhaul link. The solution proposed in this paper relies on a dynamic programming approach, implementing a cost function that balances power consumption and quality of service. The cost is then aggregated using penalties based on the energy harvested and battery charge. The implemented algorithm is demonstrated (in simulations) able to adapt the user assignment to the network load and energy production.

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Section: Resultsmentioning

confidence: 99%

Multi-Radio Access Network Assignment Using Dynamic Programming

Anis

Weiss

2019

2019 International Conference on Software, Telecommunications and Computer Networks (SoftCOM)

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“…slower) and can increase design complexity. That being said, it has been shown that under certain conditions non-power-of-2 FFTs can result in a reduction in hardware resources and power consumption [29].…”

Section: B Sub-optimal Algorithmsmentioning

confidence: 99%

A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware

Goldsmith

Crockett

Stewart

2022

IEEE Open J. Circuits Syst.

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We present a natively fixed-point filter design method that targets FPGA-based Reconfigurable Finite Impulse Response (RFIR) filters for Software Defined Radio applications. The Filter Designer is capable of reconfiguring cut-off frequencies on-the-fly at run-time; with other parameters, such as filter length and window type, configurable at compile-time. The ability to compute filter coefficients directly on FPGAs is compelling, as much lower latencies can be achieved when compared to RFIRs programmed with embedded processors. In this work we discuss several filter design techniques from the literature and investigate their suitability for implementation on FPGAs. A hybrid method combining window and frequency sampling methods is developed and implemented on a Xilinx Zynq-7000 SoC. We explore the limitations of designing filters in fixed-point arithmetic and consider the effects filter length and wordlength have on filter quality. Results show that the proposed algorithm generates good-quality filters that display stopband attenuation up to 88dB, transition bandwidths less than 1% of the sample rate, and low resource utilisation. Most notably, we found that our method is up to three orders of magnitude faster than an equivalent software implementation, with execution times as low as 2.52 µs, enabling radio applications in which latency is a principal constraint.

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FPGA Implementation of a TVWS Up- and Downconverter Using Non-Power-of-Two FFT Modulated Filter Banks

Cited by 2 publications

References 16 publications

Multi-Radio Access Network Assignment Using Dynamic Programming

Multi-Radio Access Network Assignment Using Dynamic Programming

A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware

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