Energy-efficient instruction dispatch buffer design for superscalar processors

Küçük, Gürhan; Ghose, K.; Ponomarev, Dmitry; Kogge, Peter M.

doi:10.1109/lpe.2001.945407

Cited by 25 publications

(17 citation statements)

References 3 publications

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“…One of the artifacts of a superscalar processor, where the mismatches in the comparands are much more frequent than the full matches is the issue queue [1,5]. The issue queue thus demands the use of non-traditional fast comparators that dissipate energy only (or predominantly) on a full match and little or no energy on a partial match [1,2,5].…”

Section: Non-traditional Comparatorsmentioning

confidence: 99%

“…The issue queue thus demands the use of non-traditional fast comparators that dissipate energy only (or predominantly) on a full match and little or no energy on a partial match [1,2,5]. Such designs are significantly more energy-efficient than the traditional designs.…”

Section: Non-traditional Comparatorsmentioning

confidence: 99%

“…This restriction comes from the practical limit on the number of devices in a pass transistor logic (such as the P-structure of Figure 2) and from a limit on the number of n-devices that can be connected in series structure. These limitations can be partly overcome by using a Domino-style design (as shown in [1] and [5]), but practical limits are still present. The design of Figure 2 is thus applicable to scenarios where only a small number of bits are compared, as in the instruction issue queue and associatively-addressed register alias tables (RATs).…”

Section: Non-traditional Comparatorsmentioning

confidence: 99%

“…Consequently, significant energy savings can be realized if comparators and associative logic can be designed to dissipate energy only on a full match and little or no energy on a mismatch. In recognition of this inefficiency, first noticed in [2], a series of such dissipate-on-match comparator (DMC) designs have been recently introduced [1], [5].…”

Section: Introductionmentioning

confidence: 99%

“…Section 3 describes several design alternatives for the long comparators. These designs are based on the use of several traditional comparators, several non-traditional comparator designs (as introduced in [1] or [5]) or a combination of the traditional and non-traditional designs. The choice of a specific design for a long comparator is actually dependent on the distribution of the bit patterns that are compared, which are usually obtained through microarchitectural-level simulations.…”

Section: Introductionmentioning

confidence: 99%

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Power efficient comparators for long arguments in superscalar processors

Ponomarev

Küçük

Ergin

et al. 2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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Traditional pulldown comparators that are used to implement associative addressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the comparands. As mismatches occur much more frequently than matches in many situations, such circuits are extremely energy-inefficient. In recognition of this inefficiency, a series of dissipate-on-match comparator designs have been proposed to address the power considerations. These designs, however, are limited to at most 8-bit long arguments.In this paper, we examine the designs of energy-efficient comparators capable of comparing arguments as long as 32 bits in size. Such long comparands are routinely used in the load-store queues, caches, BTBs and TLBs. We use the actual layout data and the realistic bit patterns of the comparands (obtained from the simulated execution of SPEC 2000 benchmarks) to show the energy impact from the use of the new comparators. In general, a non-trivial combination of traditional and dissipate-on-match 8-bit comparator blocks represents the most energy-efficient and fastest solution. As an example of this general approach, we show how fast and energy-efficient comparators can be designed for comparing addresses within the load-store queue of a superscalar processor.

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Section: Non-traditional Comparatorsmentioning

confidence: 99%

Section: Non-traditional Comparatorsmentioning

confidence: 99%

Section: Non-traditional Comparatorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Power efficient comparators for long arguments in superscalar processors

Ponomarev

Küçük

Ergin

et al. 2003

Proceedings of the 2003 International Symposium on Low Power Electronics and Design - ISLPED '03

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Energy-Efficient Design of the Reorder Buffer

Ponomarev

Küçük

Ghose

2002

Lecture Notes in Computer Science

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We address the question of how one evaluates the usefulness of a heuristic program on a particular input. If theoretical tools do not allow us to decide for every instance whether a particular heuristic is fast enough, might we at least write a simple, fast companion program that makes this decision on some inputs of interest? We call such a companion program a timer for the heuristic. Timers are related to program checkers, as de ned by Blum 3], in the following sense: Checkers are companion programs that check the correctness of the output produced by (unproven but bounded-time) programs on particular instances; timers, on the other hand, are companion programs that attempt to bound the running time on particular instances of correct programs whose running times have not been fully analyzed. This paper provides a family of de nitions that formalize the notion of a timer and some preliminary results that demonstrate the utility of these de nitions.

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Low power wide gates for modern power efficient processors

Asyaei

Peiravi

2014

Integration

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Energy-efficient instruction dispatch buffer design for superscalar processors

Cited by 25 publications

References 3 publications

Power efficient comparators for long arguments in superscalar processors

Power efficient comparators for long arguments in superscalar processors

Energy-Efficient Design of the Reorder Buffer

Low power wide gates for modern power efficient processors

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