The interfacing of soft and hard electronics is a key challenge for flexible hybrid electronics. Currently, a multisubstrate approach is employed, where soft and hard devices are fabricated or assembled on separate substrates, and bonded or interfaced using connectors; this hinders the flexibility of the device and is prone to interconnect issues. Here, a single substrate interfacing approach is reported, where soft devices, i.e., sensors, are directly printed on Kapton polyimide substrates that are widely used for fabricating flexible printed circuit boards (FPCBs). Utilizing a process flow compatible with the FPCB assembly process, a wearable sensor patch is fabricated composed of inkjet‐printed gold electrocardiography (ECG) electrodes and a stencil‐printed nickel oxide thermistor. The ECG electrodes provide 1 mVp–p ECG signal at 4.7 cm electrode spacing and the thermistor is highly sensitive at normal body temperatures, and demonstrates temperature coefficient, α ≈ –5.84% K–1 and material constant, β ≈ 4330 K. This sensor platform can be extended to a more sophisticated multisensor platform where sensors fabricated using solution processable functional inks can be interfaced to hard electronics for health and performance monitoring, as well as internet of things applications.

Modern microprocessors employ one or two levels of on-chip caches to bridge the burgeoning speed disparities between the processor and the RAM. These SRAM caches are a major source of power dissipation. We investigate architectural techniques, that do not compromise the processor cycle time, for reducing the power dissipation within the on-chip cache hierarchy in superscalar microprocessors. We use a detailed register-level simulator of a superscalar microprocessor that simulates the execution of the SPEC benchmarks and SPICE measurements for the actual layout of a 0.5 micron, 4metal layer cache, optimized for a 300 MHz. clock. We show that a combination of subbanking, multiple line buffers and bit-line segmentation can reduce the on-chip cache power dissipation by as much as 75% in a technology-independent manner.

We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energycacheaxchitectures. The analyticalmodelsusethenm time statistics such as hit/miss c4mnt.s. fraction ofread/write requests aud assume stcdastical distributions for signal values. These models are validated by comparing the power estimated using these models against the power estimated using a detailed simulator called CAPE (CAache Power Estimator). The analytical models for conventional caches are found to be accurate to within 2% error. However, these analyticalm&ls over-predict the dissipations of low-power caches by as much as 30%. The inaccuracies can be attributed to correlated signal vales and locality of reference, both of which are exploited in making some cache organizations energy efficient.

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