Energy‐efficient LDPC codec design using cost‐effective early termination scheme

Lin, Cheng-Hung; Wu, Yuan-Syun; Song, Chen-Pei

doi:10.1049/iet-cdt.2018.5074

Cited by 4 publications

(7 citation statements)

References 20 publications

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“…In contrast to the limited applicability mentioned in [15], our system is capable of seamlessly adapting to different standards with minimal verification required. Therefore, this stands in contrast to previous studies such as [17] and [22], which faced limitations in terms of applicability and required extensive verification processes. The flexibility of our system allows for its efficient deployment in diverse scenarios, accommodating a wide range of frequency requirements and standards.…”

Section: System Integration Basedmentioning

confidence: 82%

“…However, for Near-Earth communications, a preprocessing algorithm was introduced, which adds complexity to the encoding process and may require additional computational resources. Lastly, the authors in [22] offered an energyefficient codec design using a rate-0.91 systematic QC-LDPC code, incorporating a cost-effective early termination scheme that achieved significant energy reduction (54.6%) with minimal area overhead compared to no early termination. The chip operated at 278 MHz and achieved the best decoding energy efficiency and high throughput.…”

Section: Related Workmentioning

confidence: 99%

“…Based on this, the proposed power controller in our study demonstrates an advantage in terms of power consumption compared to previous studies that utilized different technology nodes. For instance, studies using 65-nm [13,15], 28-nm [16,18], or even 90-and 45-nm CMOS technology [17,22] may experience higher power consumption compared to our proposed approach. By leveraging the benefits of 16-nm CMOS technology, our power controller contributes to reducing overall power consumption, making it a promising solution for efficient power management in LDPC encoders.…”

Section: Comparative Analysis Cmos Technology Basedmentioning

confidence: 99%

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Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

2023

IJIES

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Low density parity check (LDPC) codes are highly regarded for their exceptional error correction capabilities, making them a preferred choice for error correction coding (ECC) in modern communication standards. These codes are implemented in specialized integrated circuits (ICs) that facilitate data transmission. However, the power requirements of complementary metal-oxide-semiconductor (CMOS) circuits, which operate across a wide frequency range, present a significant challenge for future communication systems. To address this challenge, this paper proposes a novel multi-frequency power reduction strategy for LDPC encoders. The strategy utilizes dynamic voltage and frequency scaling (DVFS), a well-established power reduction method in CMOS circuits. By combining DVFS with fuzzy logic control, the system optimizes the voltage supplied to the LDPC encoder, achieving substantial power reduction while maintaining coding efficiency, flexibility, and performance. The proposed approach dynamically adjusts the encoder's voltage levels based on real-time conditions, ensuring efficient power consumption across different frequencies. This innovative strategy aims to overcome the power challenges faced by future communication generations, which have been largely overlooked in previous research efforts. This paper aims to assess the effectiveness of a multi-frequency power reduction strategy for LDPC encoders. Through extensive analysis and evaluations, it demonstrates significant power reduction while maintaining LDPC coding efficiency. These findings contribute to the development of power-efficient LDPC encoder designs, meeting the evolving needs of communication systems. Results reveal the system's performance across different frequency ranges. In the lowfrequency range (1 MHz to 100 MHz), a remarkable 90% power reduction is achieved. In the medium-frequency range (100 MHz to 1 GHz), the reduction is 50%, while in the high-frequency range (1 GHz to 5 GHz), it reaches 20% to 14.5%. Notably, the system operates most effectively in the low and medium frequency range, providing substantial power savings. These results highlight the potential of the multi-frequency power reduction strategy for LDPC encoders in addressing power challenges across different frequencies. The significant power reduction achieved demonstrates its effectiveness and adaptability to varying frequency demands. This contributes to the development of power-efficient LDPC encoder designs, optimizing performance and energy consumption in various communication systems.

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Section: System Integration Basedmentioning

confidence: 82%

Section: Related Workmentioning

confidence: 99%

Section: Comparative Analysis Cmos Technology Basedmentioning

confidence: 99%

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Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

2023

IJIES

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“…Furthermore, these hardware efficient decoding algorithms should offer sufficient parallelism such that their computational capabilities can be fully exploited. In particular, many recent studies have shown that low complex LDPC decoding schemes can minimize the critical path delay and routing congestion, which in turn can facilitate high throughput per silicon area 29 . The overall summary of the recent research issues related to the efficient design approach of LDPC decoding algorithms is shown in Figure 3.…”

Section: Issues and Challenges Of Ldpc Decodingmentioning

confidence: 99%

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Roberts¹,

Kumari

Anguraj³

2021

Int J Communication

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Summary Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements in error control coding methods have seen a huge surge in using low‐density parity‐check (LDPC) code‐based decoding algorithms to solve imperative issues related to reliable data transmission and reception. Till date, extensive research efforts have been consistently being made on LDPC codes which focus on algorithm‐driven and hardware‐realization‐based approaches. The main intension of this research work is to provide an extensive systematic elucidation on the recent advancements in LDPC decoding algorithms. In addition, a thorough performance evaluation and analysis of several outstanding LDPC decoding techniques is presented. Finally, conclusions are drawn by summarizing the important research findings, interesting open problems, current challenges and broader perspectives for future directions of research.

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“…e early termination (ET) method terminates the decoding process as early as possible before reaching the maximum number of iterations, and it can therefore increase the decoding method's convergence rate. e authors in [32][33][34][35][36] provided many useful ET methods that have reduced the BP decoder's complexity by avoiding unnecessary decoding processes. At present, the standard ε rule and the ET scheme of Hx T � 0 are two primary stopping methods for ADMM decoding.…”

Section: Introductionmentioning

confidence: 99%

Novel Early Termination Method of an ADMM-Penalized Decoder for LDPC Codes in the IoT

Wang

2022

Security and Communication Networks

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As a critical communication technology, low-density parity-check (LDPC) codes are widely concerned with the Internet of things (IoT). To increase the convergence rate of the alternating direction method of multiplier (ADMM)-penalized decoder for LDPC codes, a novel early termination (ET) method is presented by computing the average sum of the hard decision (ASHD) during each ADMM iteration. In terms of the flooding scheduling and layered scheduling ADMM-penalized decoders, the simulation results show that the proposed ET method can significantly reduce the average number of iterations at low signal-to-noise ratios (SNRs) with negligible decoding performance loss.

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Energy‐efficient LDPC codec design using cost‐effective early termination scheme

Cited by 4 publications

References 20 publications

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

Designing A Multi-Frequency Low Power Low-Density Parity Check (LDPC) Encoder with A Dynamic Voltage and Frequency Scaling (DVFS) Approach

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Novel Early Termination Method of an ADMM-Penalized Decoder for LDPC Codes in the IoT

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