Here, the authors propose an energy-efficient codec design using a rate-0.91 systematic quasi-cyclic-low-density parity-check (QC-LDPC) code. A cost-effective early termination (ET) scheme is presented for efficiently terminating the decoding iterations and maintaining desirable correcting performance. Compared with no ET scheme, the cost-effective ET scheme achieves 54.6% energy reduction with 1.7% area overhead. Finally, the proposed QC-LDPC codec employing the costeffective ET scheme is implemented in a prototyping chip of 9.86 mm 2 core area using the TSMC 90 nm CMOS technology. Compared with the other decoder chips, the prototyping codec operating at 278 MHz achieves the best decoding energy efficiency of 156 pJ/bit with a high decoding throughput of 4.3 Gbps. The prototyping codec also achieves a high encoding throughput of 4.4 Gbps.

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