Energy-efficient Motion Estimation using Error-Tolerance

Varatkar,; Shanbhag,

doi:10.1109/lpe.2006.4271817

Cited by 22 publications

(16 citation statements)

References 18 publications

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“…Suppose we use approximate FAs for 7 LSBs. Then, Cin [7] = Cout [6]. Note that Cout [6] is approximate.…”

Section: Approximate Addersmentioning

confidence: 99%

“…Then, Cin [7] = Cout [6]. Note that Cout [6] is approximate. Applying this approximation to our present example, we find that carry propagation from bit 0 to bit 6 is entirely eliminated.…”

Section: Approximate Addersmentioning

confidence: 99%

“…Few works that focus on low-power design through approximate computing at the algorithm and architecture levels include algorithmic noise tolerance (ANT) [3]- [6], significance driven computation (SDC) [7]- [9], and nonuniform voltage overscaling (VOS) [10]. All these techniques are based on the central concept of VOS, coupled with additional circuitry for correcting or limiting the resulting errors.…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of Booth Multiplier using Approximate Adders

Keskar¹,

Mote²

2015

International Journal of Innovative Research in Electrical, Ele

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Low power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. In most multimedia applications, human beings can gather useful information from slightly erroneous outputs. Therefore, we do not need to produce exactly correct numerical outputs. Previous research in this context exploits error resiliency primarily through voltage overscaling, utilizing algorithmic and architectural techniques to mitigate the resulting errors. In this paper, we propose logic complexity reduction at the transistor level as an alternative approach to take advantage of the relaxation of numerical accuracy. We demonstrate this concept by proposing various imprecise or approximate full adder cells with reduced complexity at the transistor level, and utilize them to design approximate multi-bit adders. In addition to the inherent reduction in switched capacitance, our techniques result in significantly shorter critical paths, enabling voltage scaling.

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“…Suppose we use approximate FAs for 7 LSBs. Then, Cin [7] = Cout [6]. Note that Cout [6] is approximate.…”

Section: Approximate Addersmentioning

confidence: 99%

“…Then, Cin [7] = Cout [6]. Note that Cout [6] is approximate. Applying this approximation to our present example, we find that carry propagation from bit 0 to bit 6 is entirely eliminated.…”

Section: Approximate Addersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design and Implementation of Booth Multiplier using Approximate Adders

Keskar¹,

Mote²

2015

International Journal of Innovative Research in Electrical, Ele

View full text Add to dashboard Cite

show abstract

“…Previous works that focus on low-power design through approximate computing at the algorithm and architecture levels include algorithmic noise tolerance (ANT) [3]- [6], significance driven computation (SDC) [7]- [9], and non-uniform voltage over scaling (VOS) [10]. All these techniques are based on the central concept of VOS, coupled with additional circuitry for correcting or limiting the resulting errors.…”

Section: Introductionmentioning

confidence: 99%

Quality Improvement and Power Reduction in Digital Signal Processing Using Approximate Adders

Edavackal¹,

Mahalakshmi²

2014

IOSRJVSP

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“…We extend recent work in [18] by providing analytical solutions based on modelling of computation errors due to voltage over scaling (VOS) and sub-sampling (SS). Results show that our solutions provide significantly better performance in the sense of rate increase for fixed QP , e.g., less than 5% increase, while in [18] the rate increase could be as high as 20%.…”

Section: Introductionmentioning

confidence: 99%

Power Efficient Motion Estimation using Multiple Imprecise Metric Computations

Chong

Ortega

2007

Multimedia and Expo, 2007 IEEE International Conference On

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In this paper, we propose power efficient motion estimation (ME) using multiple imprecise sum absolute difference (SAD) metric computations. We extend recent work in [18] by providing analytical solutions based on modelling of computation errors due to voltage over scaling (VOS) and sub-sampling (SS). Results show that our solutions provide significantly better performance in the sense of rate increase for fixed QP , e.g., less than 5% increase, while in [18] the rate increase could be as high as 20%. Our analysis also allows us to compare different ME algorithms (e.g., full search vs. a fast algorithm) and SAD computation architectures (parallel vs. serial) in terms of their robustness to imprecise metric computations and their power efficiency. Finally, we demonstrate that additional power savings can be achieved by removing redundancy between the various computations.

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Energy-efficient Motion Estimation using Error-Tolerance

Cited by 22 publications

References 18 publications

Design and Implementation of Booth Multiplier using Approximate Adders

Design and Implementation of Booth Multiplier using Approximate Adders

Quality Improvement and Power Reduction in Digital Signal Processing Using Approximate Adders

Power Efficient Motion Estimation using Multiple Imprecise Metric Computations

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