Power Efficient Motion Estimation using Multiple Imprecise Metric Computations

Chong, In Suk; Ortega, Antonio

doi:10.1109/icme.2007.4285083

Cited by 5 publications

(3 citation statements)

References 17 publications

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“…The effects of errors due to defects in some functional blocks of a MPEG encoder on the performance of the circuits have been extensively studied [Cheong and Ortega 2007;Chong and Ortega 2007;Chong et al 2006;Chung and Ortega 2005]. These results indicate that for about 50% of those defects that can be modeled as a single or double stuck-at fault, the resulting defective MPEG circuits generate acceptable performance.…”

Section: Introductionmentioning

confidence: 80%

Error Rate Estimation for Defective Circuits via Ones Counting

Pan¹,

Breuer

2012

ACM Trans. Des. Autom. Electron. Syst.

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With VLSI circuit feature size scaling down, it is becoming more difficult and expensive to achieve a desired level of yield. Error-tolerance employs defective chips that occasionally produce erroneous yet acceptable results in targeted applications, and has been proposed as one way to increase effective yield. These chips are characterized by criteria set by specific applications. Error rate, an upper-bound on how frequent errors occur at an output, is one such criterion. In this article we focus on the following problem: given a combinational logic circuit that is defective, and hence occasionally produces an erroneous output, how can we determine the error rate of each output line by using ones counting? The results of this work can also be used for runtime error estimation in aging systems and in environments where soft-errors are produced. ACM Reference Format:Pan, Z. and Breuer, M. A. 2012. Error rate estimation for defective circuits via ones counting. ACM Trans.

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Section: Introductionmentioning

confidence: 80%

Error Rate Estimation for Defective Circuits via Ones Counting

Pan¹,

Breuer

2012

ACM Trans. Des. Autom. Electron. Syst.

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“…Many of them are related to the specific case of an MPEG encoder. Different methods of power-reduction include algorithmic modifications [1], [2], voltage over-scaling [3], and imprecise computation of metrics [4]. The introduction of approximate computing techniques has opened up entirely new opportunities in building low-power video compression architectures.…”

Section: Related Workmentioning

confidence: 99%

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Raha

Jayakumar

Raghunathan

2016

IEEE Trans. VLSI Syst.

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The field of approximate computing has received significant attention from the research community in the past few years, especially in the context of various signal processing applications. Image and video compression algorithms, such as JPEG, MPEG, and so on, are particularly attractive candidates for approximate computing, since they are tolerant of computing imprecision due to human imperceptibility, which can be exploited to realize highly power-efficient implementations of these algorithms. However, existing approximate architectures typically fix the level of hardware approximation statically and are not adaptive to input data. For example, if a fixed approximate hardware configuration is used for an MPEG encoder (i.e., a fixed level of approximation), the output quality varies greatly for different input videos. This paper addresses this issue by proposing a reconfigurable approximate architecture for MPEG encoders that optimizes power consumption with the goal of maintaining a particular Peak Signal-to-Noise Ratio (PSNR) threshold for any video. Toward this end, we design reconfigurable adder/subtractor blocks (RABs), which have the ability to modulate their degree of approximation, and subsequently integrate these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder. We propose two heuristics for automatically tuning the approximation degree of the RABs in these two modules during runtime based on the characteristics of each individual video. Experimental results show that our approach of dynamically adjusting the degree of hardware approximation based on the input video respects the given quality bound (PSNR degradation of 1%-10%) across different videos while achieving a power saving up to 38% over a conventional nonapproximated MPEG encoder architecture. Note that although the proposed reconfigurable approximate architecture is presented for the specific case of an MPEG encoder, it can be easily extended to other DSP applications.Index Terms-Approximate circuits, approximate computing, low power design, quality configurable.

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“…Given the aforementioned techniques for reduced precision arithmetic ( § 1.7.1), probabilistic computation ( § 1.7.3), hardware architectures and software techniques that take license with correctness ( § 1.7.4 and § 1.7.5), and language-level facilities for specifying how much incorrectness applications can tolerate ( § 1.7.6), a natural question is, which applications can best harness the possibilities afforded by these hardware and software innovations? Several proposals for potential application of such "good-enough" computation have been made in the research literature , Chippa et al, 2010, Breuer, 2010, 2005a, Meng et al, 2009, Chong and Ortega, 2007, Li and Yeung, 2007, Mohapatra et al, 2009, Breuer, 2005b, Salesin et al, 1989, however no consensus yet exists on a standard set of applications for evaluating proposed hardware and software techniques. Similarly, no commonly agreed-upon metrics exist for evaluating the degree to which behavior of benchmarks may deviate from correctness.…”

Section: Applications Of "Good-enough" Computation In Algorithms and mentioning

confidence: 99%

Error-Efficient Computing Systems

Stanley-Marbell

Rinard

2017

FNT in Electronic Design Automation

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This survey explores the theory and practice of techniques to make computing systems faster or more energy-efficient by allowing them to make controlled errors. In the same way that systems which only use as much energy as necessary are referred to as being energy-efficient, you can think of the class of systems addressed by this survey as being error-efficient: They only prevent as many errors as they need to. The definition of what constitutes an error varies across the parts of a system. And the errors which are acceptable depend on the application at hand. In computing systems, making errors, when behaving correctly would be too expensive, can conserve resources. The resources conserved may be time: By making some errors, systems may be faster. The resource may also be energy: A system may use less power from its batteries or from the electrical grid by only avoiding certain errors while tolerating benign errors that are associated with reduced power consumption. The resource in question may be an even more abstract quantity such as consistency of ordering of the outputs of a system. This survey is for anyone interested in an end-to-end view of one set of techniques that address the theory and practice of making computing systems more efficient by trading errors for improved efficiency.

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Power Efficient Motion Estimation using Multiple Imprecise Metric Computations

Cited by 5 publications

References 17 publications

Error Rate Estimation for Defective Circuits via Ones Counting

Error Rate Estimation for Defective Circuits via Ones Counting

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Error-Efficient Computing Systems

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