Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding

R, Nirmaladevi; Seshasayanan, R.

doi:10.1007/s10586-017-1162-3

Cited by 3 publications

(8 citation statements)

References 21 publications

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“…When these three points are connected, it forms a tetrahedron which acts as virtual boundary conditions for the adders. Within this boundary limit, an adder has a superior performance, the Ling Adder Ling (1981) 1 XOR 1 2(log 2 n)11MUX Conditional carry adder, Cheng and Cheng (2006) 11(log 2 n)MUX 1 1 XOR PPA-Kogge-Stone 11(log 2 n)12 XOR PPA -Sklansky 11(log 2 n)1 2 XOR PP_ HK, Ruiz and Granda (2008) (log 2 n) 1 1MUX 1 1 XNOR Hybrid adder Nirmaladevi and Seshasayanan (2017) 1 XOR 1 3 1 1MUX1(n/4 À 1) Proposed hybrid architecture (log 2 n) 1 1 1 2 XOR selection point would indicate the prediction of performance of the designed adder. The hybrid design styles are always seeking for superior performance; hence, combining the adder architectures would suggest a different family of adder which is expected to close to the ideal prefix architecture.…”

Section: Resultsmentioning

confidence: 99%

“…In this design, the number of logic gates is increased and consumes a large amount of power because of the massive overlap between the prefix sub-terms being pre-computed. Ruiz and Granda (2008) Another hybrid parallel architecture has been proposed for the generation of 3X multiple (Nirmaladevi and Seshasayanan, 2017), by recognizing that the carry signals have symmetry during the addition of 2X1X. As carry signals are the main cause for the propagation delay in binary addition, this symmetry is exploited for rapid propagation of carry signals.…”

Section: Related Workmentioning

confidence: 99%

“…Though the pseudo carry signals are generated simultaneously, there is a definite time delay involved in this method for the generation of pseudo carry signals. Nirmaladevi and Seshasayanan (2017) compared the results with the state of the art adders and achieved an improvement of 62, 22 and 3% in delay for 32 bits for RCA, CLA and PPA_KS, respectively. As 3X = 2X 1 X, the occurrence of the multiplicand bits exhibit a symmetry, this has been exploited for every 4 bit group of multiplicand to generate the pseudo carry signals (Nirmaladevi and Seshasayanan, 2017).…”

Section: Related Workmentioning

confidence: 99%

“…Nirmaladevi and Seshasayanan (2017) compared the results with the state of the art adders and achieved an improvement of 62, 22 and 3% in delay for 32 bits for RCA, CLA and PPA_KS, respectively. As 3X = 2X 1 X, the occurrence of the multiplicand bits exhibit a symmetry, this has been exploited for every 4 bit group of multiplicand to generate the pseudo carry signals (Nirmaladevi and Seshasayanan, 2017). Further, it is noticed that the expansion of carry in equation ( 2) has recurrence symmetry in every alternate terms.…”

Section: Related Workmentioning

confidence: 99%

“…This proposed 3X hybrid adder architecture is implemented by exploiting the recurrence symmetry, whereas in Nirmaladevi and Seshasayanan (2017), the occurrence symmetry is exploited for Pseudo carry (Cp) generation as explained in Section 2 [equations ( 7)-( 9)], and the critical path is minimized by adopting Ling prefix structure (Nirmaladevi and Seshasayanan, 2017). In contrast with that, this proposed work adopts the concept of simultaneous generation odd and even carry signals by parallel carry tree structure (Ruiz and Granda, As the primary cells in this PHA is modified to share the input bits, the Sklansky architecture can easily be adopted in the higher logic levels.…”

Section: Salient Features Of the Proposed Hybrid Architecturementioning

confidence: 99%

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Hybrid parallel adder for 3X multiple generation in radix-8 booth encoding using fast carry tree structure

Ramu¹,

Ramachandran²

2020

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Purpose In most commercial processors, enhancing the speed of multiplication using radix-8 booth encoding is the preferred option. In radix-8 architecture, the 3X(= 2X + X) multiple generation is a major bottleneck. This paper aims to propose a parallel implementation scheme recognizing the symmetry in the carry recurrence equations of 3X multiples. The proposed architecture evaluates the odd (H) and even (K) carry signals separately. As prefix tree structure offers fast carry propagation, the parallel implementation is based on a hybrid style of two popular prefix architectures. Design/methodology/approach The performance of the proposed architecture is evaluated using Cadence TSMC 180 nm library. A comparison of performance parameters with other architectures has been carried out to highlight the architectural advantages of the proposed architecture. Findings A comparison of performance parameters with others shows that the proposed architecture has a reduced critical path and a commensurate improvement in delay for a bit width of 64. It is shown that up to 32 bits, this parallel architecture has a superior performance and would be the appropriate choice for Application Specific Integrated Circuit (ASIC) implementation. It has also been suggested that higher-order bit widths could be implemented using a modular arrangement. Originality/value This paper proposes a new parallel architecture for hard multiple (3X) generation in Radix-8 Booth encoding. As the multiplication is the key operation in digital signal processors, this type of high-speed architectures gains importance in the future processor design. Defence applications such as target finding and multiple target recognitions and image processing applications necessitate this type of high-speed multipliers. Also, it is appropriate for the ASIC implementation. The authors would like to mention that this paper is not yet published anywhere, and it is the research paper of Dr R. Nirmaladevi.

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Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Salient Features Of the Proposed Hybrid Architecturementioning

confidence: 99%

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Hybrid parallel adder for 3X multiple generation in radix-8 booth encoding using fast carry tree structure

Ramu¹,

Ramachandran²

2020

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Gecikme, alan, güç ve enerji açısından hibrit paralel toplayıcılar için karşılaştırmalı bir performans değerlendirmesi

Avcı

Özarpa

Aydın

2023

Gazi Üniversitesi Mühendislik Mimarlık Fakültesi Dergisi

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Gelişen teknoloji çağında modern elektronik sistemlerde daha hızlı uygulamalar daha az enerji tüketimi, alan, güç ve gecikme taleplerini artırmaktadır. Bu araştırma çalışması, paralel toplayıcıların çeşitli sınıflarını ve yapılmış akademik çalışmalardaki hibrit paralel toplayıcıları sunmaktadır. Bu çalışmada önerilen modellerin gecikme, alan, enerji ve güç tüketimi için hibrit paralel toplayıcı performans kriterleri karşılaştırmalı olarak araştırılmıştır. Ayrıca, bu çalışmada araştırılmış olan hibrit paralel toplama araçlarının belirli kriterlere ilişkin performans sonuçları paylaşılmıştır. Elde edilen karşılaştırmalı sonuçlara göre daha az gecikme, alan, güç ve enerji tüketimine sahip hibrit paralel toplayıcı devreleri tasarlanabilecektir. Bu sonuçlara bakılarak çalışma yapılacak alanlar için dizayn yapılacak işlemcilerin toplayıcılar açısından veriler göz önüne alınarak hibrit model seçimleri yapılabilmesi mümkün hale gelecektir. Tablo 1.’de verilen karşılaştırmalı sonuçlar araştırmacılar tarafından deneyler yapılarak elde edilmiş sonuçları göstermektedir. Hibrit paralel toplayıcılar üzerine yapılan bu araştırmada genel olarak tüm uzunluklardaki bitler ele alınmaya çalışılmıştır. Bu paralel toplayıcılar yapılan araştırmalara göre farklı alan, gecikme, güç ve enerji açısından hibrit paralel toplayıcıların deneysel sonuçları bir araya getirilerek karşılaştırmalı analizleri verilmiştir.

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Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

2024

Teh. vjesn.

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This research focuses on critical hardware components of an Internet of Things (IoT) system for reconfigurable processing systems. Single-Instruction Multiple-Data (SIMD) processors have recently been utilized to preprocess data at energy-constrained sensor nodes or IoT gateways, saving significant energy and bandwidth for transmission. Using traditional CPU-based systems to implement machine learning algorithms is inefficient in terms of energy consumption. In the proposed method Single-Instruction Multiple-Data (SIMD) processors are assembled by scaling the largest possible operand value subunits into direct access to the internal memory, where the carry output of each unit is conditionally fed into the next unit based on the implementation of the SIMD Processor design for Internet of Things applications. Each method has evaluated sub-operations that contribute considerably to the overall potential of the design. If the single register file can complete the intended action, a zero (one)-signal is applied to each unit's carry input. Multiplexers combine two or more adders, sending the carry signal from one unit into another if additional units are necessary to compute the sum. The outcome results compare high-speed end device techniques in terms of area and power consumption. The proposed SIMD processor-based IoT healthcare monitoring system with a MIMD processor's performance analysis of comparison clearly demonstrates that the system produces decent outcomes. The suggested system has an area overhead of 85 m 2 , a power usage of 4.10 W, and a time delay of 20 ns.

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Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding

Cited by 3 publications

References 21 publications

Hybrid parallel adder for 3X multiple generation in radix-8 booth encoding using fast carry tree structure

Hybrid parallel adder for 3X multiple generation in radix-8 booth encoding using fast carry tree structure

Gecikme, alan, güç ve enerji açısından hibrit paralel toplayıcılar için karşılaştırmalı bir performans değerlendirmesi

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

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