Energy-efficient SATD for beyond HEVC

Seidel, Ismael; Bräscher, André Beims; Güntzel, José Luís; Agostini, Luciano

doi:10.1109/iscas.2016.7527362

Cited by 16 publications

(6 citation statements)

References 16 publications

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“…Table III presents these results for the proposed and related TBbased SATD architectures. In comparison with the existing 4×4 SATD architectures [15], [22], the proposed solution has competitive area, although it only takes one-fifth and onefourth of their clock periods, respectively. In the case of 8×8 SATD architectures, the proposed work is the smallest.…”

Section: Resultsmentioning

confidence: 99%

“…However, the second WHT stage uses the output of the first stage, so a buffer is needed between them if the transforms are not fully parallel. Several architecture explorations between parallel and buffer-based schemes can be found in the literature [15], [16], [21], [22]. A two-stage architecture with a TB [12] between the stages has proven to be a good tradeoff between energy consumption and area, so it was selected as basis for this work.…”

Section: Proposed Hardware Satd Implementationmentioning

confidence: 99%

“…Several FWHT-based SATD hardware architectures can be found in the literature [12]- [14]. The authors in [15], [16] investigated the usage of linear and transpose buffers between 1-D transform stages with square block sizes from 4×4 to 32×32. Transpose Buffer (TB) was reported to be more energy-efficient, although it results in greater chip area.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

Partanen

Lemmetti

Sjövall

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents the first known high-level synthesis (HLS) implementation for the Sum of Absolute Transformed Differences (SATD) calculation. The proposed hardware architecture is designed for two SATD algorithms: a widespread Fast Walsh-Hadamard Transform (FWHT-SATD) and a recently introduced Transform Exempted scheme (TE-SATD). This 2-stage architecture is made up of two 1-D Walsh-Hadamard Transform (WHT) stages and a transpose buffer (TB) between them. The chosen HLS approach cuts down design time over contemporary design methods and thereby made it feasible to implement a set of dedicated FWHT-SATD and TE-SATD architectures for 4×4, 8×8, and 16×16 pixel blocks. All these six architectures were synthesized for 28 nm and 45 nm standard cell technologies, and their area and energy consumptions were analysed. TE-based implementations provide 6.0-8.3% total cell area savings and 6.9-12.7% better energy-efficiency than traditional FWHT approaches. Our proposal is the first to introduce TE-SATD architectures for up to 16×16 blocks and each of these tailored architectures was shown to provide better trade-off between silicon area and performance than their reference implementations.

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Section: Resultsmentioning

confidence: 99%

Section: Proposed Hardware Satd Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

Partanen

Lemmetti

Sjövall

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…These works were synthesized to 45nm ASIC technology. Other works include algorithms development for SATD [12,13] and efficient hardware architectures [14][15][16]. The work in [17] presents an approach to explore the design space of HEVC transform.…”

Section: Introductionmentioning

confidence: 99%

“…This is also similar to the work in [19] that focuses on size 8x8 only. The work in [20] attempts at designing all sizes from 4x4 to 32x32. However, the units are designed separately with the main objective is to evaluate the growth impact of the transpose buffers and how linear buffers could be used instead for better resource utilization.…”

Section: Introductionmentioning

confidence: 99%

Hardware design of a scalable and fast 2-D hadamard transform for HEVC video encoder

Ney

Rahman

Awab

et al. 2019

IJEECS

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<span>This paper presents the hardware design of a 2-dimensional Hadamard transform used the in the rate distortion optimization module in state-of-the-art HEVC video encoder. The transform is mainly used to quickly determine optimum block size for encoding part of a video frame. The proposed design is both scalable and fast by 1) implementing a unified architecture for sizes 4x4 to 32x32, and 2) pipelining and feed through control that allows high performance for all block sizes. The design starts with high-level algorithmic loop unrolling optimization to determine suitable level of parallelism. Based on this, a suitable hardware architecture is devised using transpose memory buffer as pipeline memory for maximum performance. The design is synthesized and implemented on Xilinx Kintex Ultrascale FPGA. Results indicate variable performance obtained for different block sizes and higher operating frequency compared to a similar work in literature. The proposed design can be used as a hardware accelerator to speed up the rate distortion optimization operation in HEVC video encoders.</span>

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The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

Silveira

Paim

Abreu

et al. 2021

Circuits Syst Signal Process

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Energy-efficient SATD for beyond HEVC

Cited by 16 publications

References 16 publications

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding

Hardware design of a scalable and fast 2-D hadamard transform for HEVC video encoder

The 4-2 Fused Adder–Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures

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