Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder

Abstract

This paper presents a 1024-bit self-adaptive memory address decoder based on Dual Mode Logic (DML) design style to allow working in two modes of operation (i.e., dynamic for high-performance and static for energy-saving). The main novelty of this work relies on the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages. When performance is the primary target, the mixed operating mode is enabled, and the self-adjustment mechanism identifies at run time the logic gates that have to work in the energy-efficient mode (i.e., static mode), while those belonging to the critical path operate in the faster dynamic mode. Moreover, our address decoder can run in the fully static mode for the lowest energy consumption when speed is not a primary concern. A 65 nm CMOS technology was exploited to simulate and compare our solution with other logically equivalent dynamic and static designs. Operated in the mixed mode, the proposed circuit exhibits negligible speed reduction (8.7%) in comparison with a dynamic logic based design while presenting significantly reduced energy consumption (28%). On the contrary, further energy is saved (29%) with respect to conventional logic styles when our design runs in its energy efficient mode.

Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective

“…Most of these electronic devices of reduced size target energy efficiency since reducing the power consumption directly translates into a longer battery lifetime [1][2][3][4][5][6][7][8]. Supply voltage down-scaling is an effective method to achieve a minimum energy operation for relaxed-performance applications [9][10][11][12]. Therefore, ultra-low-power circuits can be achieved with an ultra-low-voltage (ULV) operation near the subthreshold region.…”

Design of Ultra-Low Voltage/Power Circuits and Systems

“…In the above context, this Special Issue features five research papers [17][18][19][20][21] that present original contributions for a wide range of applications, including image sensors, sensor interfaces, cryogenic computing, deep neural networks, and memory design. These five papers are briefly summarized as follows.…”

“…The obtained results show that the circuit is able to operate at supply voltages down to 0.5 V. A 10-input/10-output implementation occupies a chip area of 2570 µm 2 with a power consumption of only 3 µW, thus resulting in a very compact and energy-efficient solution as compared to digital implementations. K. Vicuña et al [21] presented a 1024 bit self-adaptive memory address decoder based on the Dual Mode Logic (DML) design style to allow working in two modes of operation, i.e., dynamic for high-performance and static for energy-saving. The main novelty of the proposal concerns the design of a controlling mechanism that mixes both of these modes of operation to simultaneously benefit from their inherent advantages.…”