Energy-efficient signal processing using FPGAs

Abstract

In this paper, we present techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform (FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations and through low-level simulation. For FFT, our designs dissipated an average of 60% less energy than the design from the Xilinx library and 56% less than the DSP. Our designs showed a factor of 10 improvement over the embedded processor. These results provide concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that FPGAs can achieve this performance while still dissipating less energy than the other two types of devices.

Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs

“…Power and energy consumption (8), meanwhile, have become important metrics in the last years and should be considered while designing lookup and classification schemes. In general terms, for the considered pipelined schemes, energy consumption involves both total latency and power consumed per pipeline stage [38]; both are also strongly related with (6) and (7); to this respect it can be reduced by selective clock gating.…”

Energy-efficient hardware/software co-synthesis for a class of applications on reconfigurable SoCs

“…For example, there are three possible bindings for storage elements in Virtex-II Pro, which are registers, slice based RAMs, and embedded Block RAMs (BRAMs). The experiments by Choi et al [5] show that registers and slice based RAMs have better energy efficiency for implementing small amount of storage while BRAMs have better energy efficiency for implementing large amount of storage.…”

“…We ignore this value so that P M 0 = 0. Using the power model from [5] and [23], energy dissipation M R 0 is estimated as 42.9 nJ/Kbyte. The communication between processor and memory follows certain protocols on the bus.…”

“…Task T 2 uses FFT to calculate the MVDR spectrum. We employed the various FFT designs discussed in [5] which are based on the radix-4 algorithm as well as the design from Xilinx CORE Generator. Clock gating, various degree of parallelism and memory bindings are used in these FFT designs to improve energy efficiency.…”

“…Clock gating, various degree of parallelism and memory bindings are used in these FFT designs to improve energy efficiency. V p and H p are the vertical and horizontal parallelism employed by the designs (see [5] for more details). Two different bindings, one using slice based RAMs and the other using BRAMs, were used to store the intermediate values.…”