Energy-efficient synchronous counter design with minimum hardware overhead

Katreepalli, Raghava; Haniotakis, T.

doi:10.1109/iccsp.2017.8286619

Cited by 6 publications

(3 citation statements)

References 3 publications

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“…A digital counter is an electronic device that counts how many times a specific event occurred [1][2][3][4][5][6][7][8]. Digital counters are usually driven by a clock.…”

Section: Introduction To Digital Counters 11 General Overviewmentioning

confidence: 99%

Design and Synthesis of a MOD 13 Binary Down Counter

Assim¹

2021

Preprint

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This work explains the process of designing and synthesizing a MOD 13 binary down counter using 180 nm CMOS technology transistors. The beginning of the count is a combination of 1110(2), the end of the count is 0010(2). Simulations are made at the circuit level (transient analysis) to verify that the circuit functions correctly, then the integrated circuit layout is prepared by connecting the components manually. Finally, the layout is simulated to see how the existence of parasitic resistances and capacitances affect the output signals and it is used to estimate the maximum allowable clock frequency (fclk).

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“…A digital counter is an electronic device that counts how many times a specific event occurred [1][2][3][4][5][6][7][8]. Digital counters are usually driven by a clock.…”

Section: Introduction To Digital Counters 11 General Overviewmentioning

confidence: 99%

Design and Synthesis of a MOD 13 Binary Down Counter

Assim¹

2021

Preprint

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“…Examples using this approach are given in [3,4]. The synchronous frequency divider design presented in this work eliminates the drawbacks of the design methods shown in [1][2][3][4] in terms of accumulating propagation delay through the chain of divider stages or extra gates by applying a cascaded retiming method applied to each divider stage individually so that the propagation delay through the chain of divider stages does not pile up. Consequently, the maximum operation speed is determined by the retiming of a single-divider stage regardless of the value of the frequency division factor, which makes the frequency divider faster compared to conventional synchronization methods.…”

mentioning

confidence: 99%

“…The second approach enforces the phase synchronization with combinatorial logic that conditions the divider outputs such that they become phase aligned. Examples using this approach are given in [3,4]. The synchronous frequency divider design presented in this work eliminates the drawbacks of the design methods shown in [1][2][3][4] in terms of accumulating propagation delay through the chain of divider stages or extra gates by applying a cascaded retiming method applied to each divider stage individually so that the propagation delay through the chain of divider stages does not pile up.…”

mentioning

confidence: 99%

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

Kossel,

Francese,

Brändli

et al. 2023

Electronics Letters

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A method is presented for the design of high‐speed frequency dividers in which the divided output signals are phase aligned by means of a scheme based on cascaded retiming. The objective of the design method proposed is to break the accumulation of propagation delay occurring in a divider chain that may limit the speed of the phase synchronization. Compared to alternative approaches where the phase synchronization is achieved with additional logical gates applied to the divider outputs, the authors’ approach only uses latches that are identical to those already employed in the divider chain itself without any additional synchronization logic. Hence, a better uniformity and homogeneity of the layout can be achieved, which helps improve the phase balancing. The method proposed to design synchronous dividers has been implemented in 5‐nm FinFET CMOS technology by means of a synchronous 8b‐counter providing the division factors 1/2 through 1/256. Its output phase synchronization has been verified in measurements at 10 GHz. The measured power consumption is 720 μW and the silicon area of the divider implemented is 79 μm2.

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Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications

Sanadhya¹,

Sharma²

2023

Springer Tracts in Electrical and Electronics Engineering

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Energy-efficient synchronous counter design with minimum hardware overhead

Cited by 6 publications

References 3 publications

Design and Synthesis of a MOD 13 Binary Down Counter

Design and Synthesis of a MOD 13 Binary Down Counter

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications

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