Energy Minimization Algorithm for Estimation of Clock Skew and Reception Window Selection in Wireless Networks

Gorawski, Michał; Grochla, Krzysztof; Marjasz, Rafał; Frankiewicz, Artur

doi:10.3390/s21051768

Cited by 3 publications

(1 citation statement)

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“…Verifications like static timing analysis and gate-level simulations that are all part of the simulation depend on these clock signals, simply because the state transition happens at a clock transition. The manner in which digital systems function is significantly influenced by their clocking techniques (14) . The fundamental block architecture for the wave pipeline gadgets, wherein the source and destination registers are synchronized by a common clock signal and intermediate latches are removed (9) .…”

Section: Clock Skew Minimizationmentioning

confidence: 99%

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Prasad,

Babu,

Kasiselvanathan

et al. 2024

IJST

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Objectives: This work objective is to construct an FPGA-based 16x16 Vedic multiplier and assess the performance of the multiplier using three distinct architectures: pipeline, wave pipeline, and modified wave pipeline in terms of delay and clock skew. Methods: The 16 × 16 Vedic multiplier was constructed and designed through four numbers of an 8x8 Vedic multiplier. For the 16x16 Vedic multiplier, the 3-stage pipeline and wave pipeline techniques are applied, and the delay performances of the Vedic multiplier are compared. Delay optimization: In the wave pipeline Vedic multiplier architecture, the delay is decreased by inserting the known delay on the longest path delay between the multiplier and adder. Clock skew optimization: The clock skew issue of the wave pipeline Vedic multiplier architecture is minimized by adjusting the setup time violation of the clock signal that is connected to the input and output registers. Findings: The delay performance of the Vedic multiplier was evaluated by the synthesis tools Xilinx 12.1, Xilinx ISE 14.2, and Altera, and based on the synthesis report, the Xilinx synthesis tool offers 73.71% delay performance for the pipeline approach and 53.39% for the wave pipeline approach compared to the Altera tool. Further delay is reduced by the proposed modified wave pipeline approach, which saves 2.122 ns of delay compared to the wave pipeline architecture. The clock skew performance was analyzed using the Time Quest timing analyzer tool, and it was minimized to 0.035 from 0.048 compared to the wave pipeline approach. Novelty: In this work, the modified wave pipeline approach has been applied to the existing Vedic multiplier architecture, and it offers less delay as well as less clock skew compared to the existing method. Hence, the performance of the Vedic multiplier with a modified wave pipelined approach was evaluated through a 3-tap FIR filter by applying a vibroarthrography signal. Keywords: Pipeline, Wave Pipeline, Vedic Multiplier, Clock skew, Set up violation, Altera quartex- II Time quest timing analyzer tool

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Section: Clock Skew Minimizationmentioning

confidence: 99%