Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology

Meyer-Baese, Uwe; Botella, Guillermo; Mookherjee, Soumak; Castillo, Encarnación; García, Antonio

doi:10.1016/j.micpro.2011.06.003

Cited by 7 publications

(3 citation statements)

References 13 publications

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“…There are some interesting observations based on performance of basic arithmetic operations by different processors.  Measured performance is substantially lower than the data from the manual [14][15][16][17], since no assembler code was used  GCC compiler optimization from -O0 through -O3 will take insignificant longer compilation time, however there is improvement in run time by a factor of 2.3 for  It can be seen from table 5 that total number of LUTs used have been increased by factor of 2.62 for Nios II which is much higher as compared to 1.21 for MicroBlaze+FP2  Maximum operating frequency has no impact due to addition of FP unit in any processor Overall run time is simply summation of times elapsed for individual steps. It might be useful to find the Frames per Second (FPS) a processor can process.…”

Section: Calculating Bpm and Snrmentioning

confidence: 99%

Real-time fetal ECG system design using embedded microprocessors

et al. 2016

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Monitoring the fetal ECG (FECG) gives us important information about the fetal wellbeing. FECG is a complex waveform where each of the P through T complexes provides wealth of information. The objective of this project is to develop the best state-of-art real-time FECG monitoring system using embedded microprocessors. Many researchers from various fields like signal processing, artificial intelligence, and advanced statistics, have applied different techniques to extract FECG from the mixture of MECG and other noises and calculate the FHR, with accuracy as an objective. Most of them are calculation intensive and not real-time. The proposed approach focuses mainly on real time processing, robustness and portability of the system. The work discussed here will provide a novel algorithm to extract FECG from abdominal ECG (AECG) which is mixture of FECG, MECG, and noise, and finding Fetal FHR with less number of dimensions (measurements) with the best signal-to-noise ratio. This approach is tested on different soft-core processors and results are compared with other commercial of-the-shelf (COTS) hardcore solutions, in terms of power, cost, size and speed. In the end FECG was successfully extracted and identified on the basis of BPM and SNR values calculated using this method. It was found that hard-core processor (ARM Cortex A9) has achieved the best real-time performance among all.

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Section: Calculating Bpm and Snrmentioning

confidence: 99%

Real-time fetal ECG system design using embedded microprocessors

et al. 2016

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“…Processor Designer (PD) [11], is used to generate the tool chain (including assembler, linker, simulator and debugger) of Thus the bandwidth of the shared bus and shared memory can be greatly reduced compared with the conventional multi core architecture.…”

Section: Imentioning

confidence: 99%

A novel multicore SDR architecture for smart vehicle systems

Chen

Hsu

et al. 2012

2012 12th International Conference on ITS Telecommunications

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A transceiver architecture with multi-core software defined radio (SDR) technology is proposed for the physical layer inner processing of IEEE S02.Up in intelligent transportation systems (ITS). By localizing the data transmissions between the adjacent digital signal processors (DSP), concatenate memories and concatenate buses are introduced to ease the bandwidth requirement for the data communication among multicores. The proposed transceiver architecture is verified by the electronic system-level (ESL) virtual platform with two application-specific instruction-set processors (ASIP). The high level power estimation results are also provided in this paper. To enhance of the channel estimation and equalization performance of IEEE S02.Up, the capability of the proposed architecture with the decision feedback algorithm is analyzed. Keywords-IEEE S02.Up; intelligent transportation systems (ITS);software-defined radio (SDR); application-specific instruction-set processor (ASIP); electronic system-level (ESL)

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“…The present embedded hardware systems, which are equipped with well‐organised software applications, can provide an efficient platform to execute real‐time ultrasonic imaging applications [6]. Moreover, reconfigurable hardware platforms based on FPGAs are appropriate for applications that demand low cost, low power and high flexibility [7, 8]. The embedded processing platforms comprise of system‐on‐chips (SoC) which integrate powerful embedded processors such as advanced RISC machines (ARM) with programmable hardware logics for high‐speed signal processing.…”

Section: Introductionmentioning

confidence: 99%

Hardware and software architectures for computationally efficient three‐dimensional ultrasonic data compression

Govindan

Wang

Ravi

et al. 2016

IET Circuits, Devices & Systems

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Ultrasonic industrial and medical imaging applications involve acquisition of large amount of volumetric data in real time. Therefore, data storage becomes critical in many current day applications which utilise ultrasound technology. Compressing the acquired data allows possessing minimal storage and also helps to rapidly transmit information to remote locations for expert analysis. The objective of this study is to design computationally efficient architectures for implementing discrete wavelet transform-based ultrasonic three-dimensional (3D) data compression algorithm on a reconfigurable ultrasonic system-on-chip (SoC) hardware platform. In this study, hardware and software architectures of the 3D ultrasonic compression algorithm are realised using Xilinx Zynq all programmable SoC. This study demonstrates that, compressing 33 MB of experimental ultrasonic 3D data into 0.42 MB (98.7% compression) requires only 84 ms for hardware architecture, and 1 min for software architecture, making both designs highly suitable for realtime ultrasonic imaging applications. Furthermore, the 3D compression is implemented by using Open Computing Language (OpenCL) targeted on Nvidia GT 750M graphical processing unit. OpenCL implementation of ultrasonic 3D compression algorithm completes the execution in <1 sec. This approach provides improved computational performance as that of hardware architecture, and comparable flexibility as that of software implementation.

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Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology

Cited by 7 publications

References 13 publications

Real-time fetal ECG system design using embedded microprocessors

Real-time fetal ECG system design using embedded microprocessors

A novel multicore SDR architecture for smart vehicle systems

Hardware and software architectures for computationally efficient three‐dimensional ultrasonic data compression

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