A transceiver architecture with multi-core software defined radio (SDR) technology is proposed for the physical layer inner processing of IEEE S02.Up in intelligent transportation systems (ITS). By localizing the data transmissions between the adjacent digital signal processors (DSP), concatenate memories and concatenate buses are introduced to ease the bandwidth requirement for the data communication among multicores. The proposed transceiver architecture is verified by the electronic system-level (ESL) virtual platform with two application-specific instruction-set processors (ASIP). The high level power estimation results are also provided in this paper. To enhance of the channel estimation and equalization performance of IEEE S02.Up, the capability of the proposed architecture with the decision feedback algorithm is analyzed. Keywords-IEEE S02.Up; intelligent transportation systems (ITS);software-defined radio (SDR); application-specific instruction-set processor (ASIP); electronic system-level (ESL)

No abstract