Energy Optimization of Subthreshold-Voltage Sensor Network Processors

Nazhandali, Leyla; Zhai, Bin; Olson, J.; Reeves, Anna; Minuth, M.; Helfand, R.; Pant, Sanjay; Austin, Todd; Blaauw, David

doi:10.1145/1080695.1069987

Cited by 52 publications

(39 citation statements)

References 14 publications

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“…Measurement results of the implemented prototype are presented in Section V. Finally, Section VI draws conclusions and gives insights for future sensor network processor designs. Preliminary findings related to this study were first presented in [6], [12], including some of the figures.…”

mentioning

confidence: 93%

Energy-Efficient Subthreshold Processor Design

Zhai

Pant

Nazhandali

et al. 2009

IEEE Trans. VLSI Syst.

139

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Abstract-Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation concludes that microarchitectural decisions in the subthreshold regime differ significantly from that in conventional superthreshold mode. We propose a new general-purpose sensor processor architecture, which we call the Subliminal Processor. On the circuit side, subthreshold operation is known to exhibit an optimal energy point ( min ). However, propagation delay also becomes more sensitive to process variation and can reduce the energy scaling gain. We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context. With careful library cell selection and robust static RAM design, the Subliminal Processor operates correctly down to 200 mV in a 0.13-m technology, which is sufficiently low to operate at min .Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency. Finally, we examine the variation in frequency and min across die to verify our analysis of adaptive tuning of the clock frequency and min for optimal energy efficiency.Index Terms-Sensor networks, subthreshold design, min , ultra low power design.

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mentioning

confidence: 93%

Energy-Efficient Subthreshold Processor Design

Zhai

Pant

Nazhandali

et al. 2009

IEEE Trans. VLSI Syst.

139

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“…The general purpose processor has to run the operating system (OS) routines and process interrupt http://jes.eurasipjournals.com/content/2013/1/5 handlers, which increase the execution cycles required per task. For example, a sequence of tasks of sampling sensor output, averaging the sampled data, and displaying the result in Berkeley's Mica Mote needs overhead of 781 cycles for interrupt handling and scheduling out of total 1118 execution cycles to complete the tasks, which translates into 70% overhead [10]. There have been efforts to design dedicated sensor network processors such as sensor network asynchronous processor (SNAP) [11] and second-generation sensor processor [12].…”

Section: Related Studymentioning

confidence: 99%

FPGA based wireless sensor node with customizable event-driven architecture

et al. 2013

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This article presents the design and implementation of modular customizable event-driven architecture with parallel execution capability for the first time with wireless sensor nodes using stand alone FPGA. This customizable event-driven architecture is based on modular generic event dispatchers and autonomous event handlers, which will help WSN application developers to quickly develop their applications by adding the required number of event dispatchers and event handlers as per the need of a WSN application. This architecture can handle multiple events in parallel, including high priority ones. Additionally, it provides non-preemptive operation which removes the timing uncertainty and overhead involved with interrupt-driven processor-based sensor node implementation, which is required in real-time wireless sensor networks (WSNs). Thus, higher computation power of FPGAs combined with the non-preemptive modular event-driven architecture with parallel execution capability enables a variety of new WSN applications and facilitates rapid prototyping of WSN applications. In this article, the performance of FPGA-based sensor device is compared with general purpose processor-based implementations of sensor devices. Results show that our FPGA-based implementation provides significant improvement in system efficiency measured in terms of clock cycle counts required for typical sensor network tasks such as packet transmission, relay and reception.

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“…• Subthreshold operation -By using a power supply less than the threshold voltage, systems such as the Subliminal and Phoenix processors from the University of Michigan and a subthreshold MSP430 from MIT are able to trade off performance for reduced active power consumption [11,14,13,16,6,21].…”

Section: Comparison To Related Workmentioning

confidence: 99%

An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS

Hempstead

Brooks

Wei

2011

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Over the past few years, deployments of wireless sensor networks (WSNs) have utilized nodes based on off-the-shelf general purpose microcontrollers. Reducing power consumption requires the development of Systemon-chip (SoC) implementations that must provide both energy efficiency and adequate performance to meet the demands of the long deployment lifetimes and bursts of computation that characterize WSN applications. This work takes a holistic approach and, thus, studies all layers of the design space, from the applications and architecture, to process technology and circuits. This paper introduces the emerging application space of wireless sensor networks and describes the motivation and need for a custom system architecture. The proposed design fully embraces the accelerator-based computing paradigm, including acceleration for the network layer (routing) and application layer (data filtering). Moreover, the architecture can disable the accelerators via VDD-gating to minimize leakage current during the long idle times common to WSN applications. We have implemented a system architecture for wireless sensor network nodes in 130nm CMOS. It operates at 550 mV and 12.5 MHz. Our system uses 100x less power when idle than a traditional microcontroller, and 10-600x less energy when active.

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Energy Optimization of Subthreshold-Voltage Sensor Network Processors

Cited by 52 publications

References 14 publications

Energy-Efficient Subthreshold Processor Design

Energy-Efficient Subthreshold Processor Design

FPGA based wireless sensor node with customizable event-driven architecture

An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS

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