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Abstract-Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation concludes that microarchitectural decisions in the subthreshold regime differ significantly from that in conventional superthreshold mode. We propose a new general-purpose sensor processor architecture, which we call the Subliminal Processor. On the circuit side, subthreshold operation is known to exhibit an optimal energy point ( min ). However, propagation delay also becomes more sensitive to process variation and can reduce the energy scaling gain. We conduct thorough analysis on how supply voltage and operating frequency impact energy efficiency in a statistical context. With careful library cell selection and robust static RAM design, the Subliminal Processor operates correctly down to 200 mV in a 0.13-m technology, which is sufficiently low to operate at min .Silicon measurements of the Subliminal Processor show a maximum energy efficiency of 2.6 pJ/instruction at 360 mV supply voltage and 833 kHz operating frequency. Finally, we examine the variation in frequency and min across die to verify our analysis of adaptive tuning of the clock frequency and min for optimal energy efficiency.Index Terms-Sensor networks, subthreshold design, min , ultra low power design.

Sensor network processors and their applications are a growing area of focus in computer system research and design. Inherent to this design space is a reduced processing performance requirement and extremely high energy constraints, such that sensor network processors must execute low-performance tasks for long durations on small energy supplies. In this paper, we demonstrate that subthreshold-voltage circuit design (400 mV and below) lends itself well to the performance and energy demands of sensor network processors. Moreover, we show that the landscape for microarchitectural energy optimization dramatically changes in the subthreshold domain. The dominance of leakage power in the subthreshold regime demands architectures that i) reduce overall area, ii) increase the utility of transistors, while iii) maintaining acceptable CPI efficiency. We confirm these observations by performing SPICE-level analysis of 21 sensor network processors and memory architectures. Our best sensor platform, implemented in 130nm CMOS and operating at 235 mV, only consumes 1.38 pJ/instruction, nearly an order of magnitude less energy than previously published sensor network processor results. This design, accompanied by bulk-silicon solar cells for energy scavenging, has been manufactured by IBM and is currently being tested.

Matching between PFET and NFET devices, achieved by adjusting A robust, energy efficient subthreshold (sub-Vth) processor has been the body bias differential, maximizes noise margins in the sub-Vth designed and tested in a 0.13ptm technology. The processor con-regime. Fig. 5 shows how the minimum functional Vdd (Vddlimit), a sumes InW at Vdd=I6OmV and 3.5pJ/inst at Vd,r=35OmV. Variabil-strong indicator of noise margins [6], is reduced from 180mV to ity and performance optimization techniques are investigated for 150mV when applying optimal differential. Fig. 5 also shows that sub-Vth circuits.the energy consumption of the core reaches a minimum at nearly the Keywords: subthreshold, variability, body-bias, low power same differential. Though dynamic energy is largely insensitive to