Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor

Hanson, Scott; Zhai, Bin; Seok, Mingoo; Cline, Brian; Zhou, Kevin; Singhal, M.; Minuth, M.; Olson, J.; Nazhandali, Leyla; Austin, Todd; Sylvester, Dennis; Blaauw, David

doi:10.1109/vlsic.2007.4342694

Cited by 50 publications

(28 citation statements)

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“…It has been shown in [5] that the delay variabilities present in sub-threshold circuits have fundamental impact on the design, e.g. shifting the supply voltage at which the minimum energy operation point is expected, which has been also verified by measurements [6].…”

Section: Introductionmentioning

confidence: 75%

“…Wire resistances are not taken into consideration, because they become negligible compared to the effective transistor output resistances at sub-threshold supply voltages as already pointed regarding the supply lines in [6]. To estimate the worst-case error made by omitting wire resistance, delays for the strongest inverter in the considered library have been determined using the wire resistance/capacitance combinations given for different fanouts in the wireload.…”

Section: B Model Verificationmentioning

confidence: 99%

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Timing modeling for digital sub-threshold circuits

Lotze¹,

Goppert²,

Manoli³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Despite an increasing interest in digital subthreshold circuits little research has been dedicated to timing modeling in this voltage domain so far. Especially high timing variabilities makes proper modeling necessary to allow for the prediction of timing behavior and timing yield on the path towards design automation. This paper first deals with gate timing characterization at sub-threshold voltages and a characterization waveform well resembling the actual transistor-level waveforms in this voltage domain is proposed. The error made in this abstraction step is identified and shown to be typically below 3%. Secondly, the modeling of timing variability is considered and the high correlation between gate delays due to slope propagation combined with strong non-linearities in the delay-slope dependencies are pointed out as modeling challenges. A pathbased logic-level Monte-Carlo technique, already magnitudes faster than transistor-level simulation, is applied and shown to match transistor-level Monte-Carlo simulation results better than 3% in mean and 7% in standard deviation values.

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Section: Introductionmentioning

confidence: 75%

Section: B Model Verificationmentioning

confidence: 99%

Timing modeling for digital sub-threshold circuits

Lotze¹,

Goppert²,

Manoli³

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

View full text Add to dashboard Cite

show abstract

“…Fig. 3 plots the change in power consumption of low-power LSI chips reported from 2007 to 2014 at ISSCC and VLSI Circuits [3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37], which are the most popular international conferences in the semiconductor industry. It is found that there are three domains: milliwatt, microwatt, and nanowatt.…”

Section: Trends In Circuit Technology and Energy Harvestingmentioning

confidence: 99%

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting

Morimura¹,

Oshima²,

Matsunaga³

et al. 2014

IEICE Electron. Express

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This paper describes circuit techniques for energy-harvesting technology in millimeter-size ultra-low-power batteryless wireless sensor nodes as a front end for BigData, IoT, M2M, and ambient intelligence. Power generated by energy harvester becomes as small as the nanowatt level when the size of a sensor node becomes millimeter-size. First, technical trends in low-power circuits and the portfolio of energy harvesting and circuit technology are discussed from the viewpoints of technical and application issues. Then, circuit techniques for nanowatt level wireless sensor nodes -a zero-power vibration sensing circuit, power management with MEMS switch, and an intermitted RF transmitter -are explained.

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“…These two types of variations are handled in different ways. The inter-die variation can be effectively mitigated by body biasing [14]. Thus, in this work, we account for the intra-die variation only and consider the delays follow the Gaussian distribution , .…”

Section: Timing Variabilitymentioning

confidence: 99%

Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above

Xie

Wang

Pedram

2013

Proceedings of the 23rd ACM International Conference on Great Lakes Symposium on VLSI

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Soft-edge flip-flop based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by allowing opportunistic time borrowing. The application of this technique to nearthreshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections and substrate temperature changes. This paper thus addresses the issue of variability-aware design of energy-delay optimal linear pipelines that are aimed at operating in both the near-threshold and super-threshold regimes. Precisely, this goal is achieved by deriving optimal delay line configuration included in the soft-edge flip-flop design for the near-threshold and the super-threshold operations. The key is to ensure that the same transistor sizes result in effective operation of the delay line (and hence appropriate setting of the transparency window size) in both regimes of operation under process induced variations. Experimental results demonstrate the efficacy of the proposed solution.

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Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor

Cited by 50 publications

References 0 publications

Timing modeling for digital sub-threshold circuits

Timing modeling for digital sub-threshold circuits

Ultra-low-power circuit techniques for mm-size wireless sensor nodes with energy harvesting

Variability-aware design of energy-delay optimal linear pipelines operating in the near-threshold regime and above

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