Energy-performance Exploration of a CGA-based SDR Processor

Abstract

Software-Defined Radio (SDR) provides the flexibility to enable cost-effective multi-mode terminals. However, the growing complexity of the new communication standards, which need to be executed with the reduced energy budget required by battery-powered devices, is still challenging architects. Although Coarse Grain Array (CGA) -based processors extended with domain specific instructions are considered strong candidates to undertake both the high-performance and low power, the lack of efficient methodologies to derive optimal instances of such an architecture paradigm is still a major limitation. In this paper, an extensive energy-performance exploration of a CGA-based SDR processor is presented. This approach targets sufficient relative accuracy on the optimization metrics, which assures meaningful comparisons between different instances, while the absolute accuracy is relaxed and traded off against simulation time. The balance between the different sources of architectural parallelism, such as data and instruction level parallelism is crucial in order to achieve the required performance at minimum energy cost. Accordingly, the proposed method is used to select the optimal DLP-ILP combination required to run the symbol-based baseband processing of a 100 Mbps+ WLAN (Wireless Local Area Network) receiver in a CGAbased processor. As a result, a 4 × 4 array with four ways SIMD (Single Instruction, Multiple Data) extensions is shown to be the optimal instance, providing minimum energy consumption and real-time processing guarantees.

Coarse-Grained Reconfigurable Array Architectures

“…Many DSEs have been performed within the ADRES template [7,11,32,37,42]. We present one experimental result [32] here, not to present absolute numbers but to demonstrate the large impact on performance and on energy consumption that some design choices can have.…”

“…In our experience, scaling dynamically reconfigurable CGRA architectures such as ADRES to very large arrays (8x8 or larger) does not make sense even with scalable interconnects like mesh or meshplus interconnects. Even in loops with high ILP, utilization drops significantly on such large arrays [42]. It is not yet clear what is causing this lower utilization, and there might be several reasons.…”

An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors

“…With such architectures, average IPCs over 10 can be obtained easily at what we believe to be a sweetspot for performance and energy efficiency [4,5,10,22]. As an example, consider our 11a WLAN SISO transmitter.…”

Scenario-based fixed-point data format refinement to enable energy-scalable software defined radios

“…The processor framework considered, namely ADRES [3], consists of a templated array of interconnected functional units (FU) which have a local register-file (LRF) and configuration memory (IB). A limited subset of these units is connected to a shared multi-ported register-file (Shared-RF), enabling their operation also as standard VLIW (Very Long Instruction Word) processor.…”

“…Certainly, these scenarios should be sufficiently easy to detect/distinguish at run-time. In this paper, the inner modem of a 2 antenna 200Mbps+ OFDM receiver is mapped onto a CGA processor with extensive SIMD support [3]. We will see that, by defining separate implementations for different combinations of modulation scheme and coding rate, important gains can be achieved in the average energy consumption.…”