Energy/Power Breakdown of Pipelined Nanometer Caches (90nm/65nm/45nm/32nm)

Abstract

As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essential to model these leakage effects properly. Moreover, typical microprocessor caches are pipelined to keep up with the speed of the processor, and the effects ofpipelining overhead need to be properly accounted for.In this paper, we present a detailed study of pipelined nanometer caches with detailed energy/power dissipation breakdowns showing where and how the power is dissipated within a nanometer cache. We explore a three-dimensional pipelined cache design space that includes cache size (16kB to 512kB), cache associativity (directmapped to 16-way) and process technology (9Onm, 65nrn, 45nm and 32nm).Among our findings, we show that cache bitline leakage is increasingly becoming the dominant cause of power dissipation in nanometer technology nodes. We show that subthreshold leakage is the main cause of static power dissipation, and that gate leakage is, surprisingly, not a significant contributor to total cache power, even for 32nm caches. We also show that accounting for cache pipelining overhead is necessary, as power dissipated by the pipeline elements is a significant part ofcache power.

EnCache: A DYNAMIC PROFILING-BASED RECONFIGURATION TECHNIQUE FOR IMPROVING CACHE ENERGY EFFICIENCY

“…6 Also, with each CMOS technology generation, leakage power has been dramatically increasing. 7 Hence, large LLCs spend a signi¯cant fraction of their energy in the form of leakage energy. Our experiments using 32-nm technology node have shown that for single-core and dualcore con¯gurations, the leakage energy of L2 cache is more than 95% of the total L2 cache energy c (dynamic energy þ leakage energy).…”

Modest

“…As the number of inactive (idle) transistors begins to dominate the number of active transistors [3], static energy becomes the major source of energy consumption. In order to have a thorough understanding of memory system behavior, we need to accurately account for both static and dynamic components of energy in the presence of spatio-temporal variations.…”

“…In order to have a thorough understanding of memory system behavior, we need to accurately account for both static and dynamic components of energy in the presence of spatio-temporal variations. Energy estimation in caches is possible through analytical, empirical and a combination of both methods [3,4,5,6,7]. Analytical models require a deep understanding of device-level physics while empirical models replicate the behavior of results produced by experiments on actual systems.…”

Dynamic cache reconfiguration based techniques for improving cache energy efficiency

“…To cater to the demands of the large number of cores and to bridge the widening gap between the speed of processor core and DRAM memory, large sized shared LLCs (last level caches) are being used; for example, Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage power has been increasing dramatically [8,9]. Thus, power consumption of caches is increasingly becoming a concern in modern processor design.…”

“…With increasing number of cores integrated on a single chip [5,72], the pressure on the memory system is rising and to mitigate this pressure, modern processors are using large sized LLCs; for example, Intel's 32nm, 8-core Poulson processor uses 32MB of LLC [73]. Further, with each CMOS technology generation, leakage energy consumption has been increasing exponentially [8,9] and hence, large LLCs contribute significantly to the total processor power consumption [74]. The increased levels of power consumption necessitate expensive cooling solutions which significantly increase the overall system cost and design complexity and also restrict further performance scaling.…”