Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration

Upadhyay, Navnidhi K.; Blum, Thomas; Maksymovych, Petro; Lavrik, Nickolay; Dávila, Noraica; Katine, J. A.; Ievlev, Anton V.; Chi, Miaofang; Xia, Qiangfei; Yang, Jianhua

doi:10.3389/fnano.2021.656026

Cited by 14 publications

(12 citation statements)

References 33 publications

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“…Various non-volatile memory devices, such as ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), spin-torquetransfer magnetic random access memory (STT-MRAM), and resistive switching random access memory (RRAM) have been considered for use as a memory element. [11][12][13][14][15][16][17][18][19][20][21][22] Among these devices, the RRAM exhibits outstanding characteristics, such as device scaling down, low power consumption, fast operation speed, simple structure, and high reliability.Various selection devices (SD) such as diodes, [23,24] metalinsulator-transition (MIT) devices, [25,26] ovonic threshold switch (OTS), [27][28][29] mixed-ionic-electronic-conductor (MIEC), [30,31] tunneling-oxide-based devices, [32,33] and timing selector [34] have been proposed to add the selection function to the RRAM devices. Furthermore, a 1-transistor and 1-resistor (1T1R) has been proposed as an active unit cell.…”

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confidence: 99%

“…Various selection devices (SD) such as diodes, [23,24] metalinsulator-transition (MIT) devices, [25,26] ovonic threshold switch (OTS), [27][28][29] mixed-ionic-electronic-conductor (MIEC), [30,31] tunneling-oxide-based devices, [32,33] and timing selector [34] have been proposed to add the selection function to the RRAM devices. Furthermore, a 1-transistor and 1-resistor (1T1R) has been proposed as an active unit cell.…”

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confidence: 99%

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Dot‐Product Operation in Crossbar Array Using a Self‐Rectifying Resistive Device

Jeon

Ryu

Jeong

et al. 2022

Adv Materials Inter

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unit between vector matrices, the workload of MAC with high-dimensional vector matrices increases exponentially. [4,5] Alternatively, the process-in-memory (PIM) unit, a concept inspired by the human brain, outperforms the von Neumann computing system in unstructured data processing considering it can provide a parallel MAC operation and reduces the time of the data bus between the CPU and the memory.A crossbar array (CA) type device is the most suitable and intuitive structure to achieve the PIM owing to its complex parallel connection of unit memory cells in the CA. [6][7][8] On applying the input signal (voltage bias) to the CA, the output signal (current, input voltage (V) × unit cell conductance (S)) is obtained instantly and simultaneously through each output line by Kirchhoff's law. [9,10] Owing to this "instant and simultaneous" calculation method, the CA-based PIM outperforms the serial process based von-Neumann computing in terms of the operation energy and time. Additionally, the CAbased PIM exhibits an immune response in the MAC operation with vector matrix expansion, which is suitable for processing large amounts of unstructured data.A data storage unit in the CA-based PIM should simultaneously exhibit two types of characteristics: 1) Highly reliable and low-power memory device and 2) device for selection function to suppress the interference effect from the parallel-connected neighboring cells in the CA. Various non-volatile memory devices, such as ferroelectric random access memory (FRAM), phase-change random access memory (PRAM), spin-torquetransfer magnetic random access memory (STT-MRAM), and resistive switching random access memory (RRAM) have been considered for use as a memory element. [11][12][13][14][15][16][17][18][19][20][21][22] Among these devices, the RRAM exhibits outstanding characteristics, such as device scaling down, low power consumption, fast operation speed, simple structure, and high reliability.Various selection devices (SD) such as diodes, [23,24] metalinsulator-transition (MIT) devices, [25,26] ovonic threshold switch (OTS), [27][28][29] mixed-ionic-electronic-conductor (MIEC), [30,31] tunneling-oxide-based devices, [32,33] and timing selector [34] have been proposed to add the selection function to the RRAM devices. Furthermore, a 1-transistor and 1-resistor (1T1R) has been proposed as an active unit cell. [35][36][37] However, stacking SD with RRAM can cause various practical issues. First, tailoring Reducing computational complexity is essential in future computing systems for processing a large amount of unstructured data simultaneously. Dot-product operations using crossbar array devices have attracted considerable attention owing to their simple device structure, intuitive operation scheme, and high computational efficiency of parallel operation. The resistive switching device is considered a promising candidate as the main data storage in the crossbar array owing to its highly reliable performance. In this study, a tri-layer TaO x /Al 2 O 3 /Ti:SiO x -based resistive...

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confidence: 99%

mentioning

confidence: 99%

Dot‐Product Operation in Crossbar Array Using a Self‐Rectifying Resistive Device

Jeon

Ryu

Jeong

et al. 2022

Adv Materials Inter

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“…This result indicates that the STP is absent in the Pt/TiO x /Pt selector device with surface plasma treatment. Therefore, the rough BE Pt/TiO x interface, which induces a local electric field enhancement in the TiO x layer, − is necessary for the STP of the Pt/TiO x /Pt exponential selector.…”

Section: Resultsmentioning

confidence: 99%

Frequency-Dependent Synapse Weight Tuning in 1S1R with a Short-Term Plasticity TiO_x-Based Exponential Selector

Chee

Dananjaya

Lim

et al. 2022

ACS Appl. Mater. Interfaces

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Short-term plasticity (STP) is an important synaptic characteristic in the hardware implementation of artificial neural networks (ANN), as it enables the temporal information processing (TIP) capability. However, the STP feature is rather challenging to reproduce from a single nonvolatile resistive random-access memory (RRAM) element, as it requires a certain degree of volatility. In this work, a Pt/TiO x /Pt exponential selector is introduced not only to suppress the sneak current but also to enable the TIP feature in a one selector-one RRAM (1S1R) synaptic device. Our measurements reveal that the exponential selector exhibits the STP characteristic, while a Pt/HfO x /Ti RRAM enables the long-term memory capability of the synapse. Thereafter, we experimentally demonstrated pulse frequency-dependent multilevel switching in the 1S1R device, exhibiting the TIP capability of the developed 1S1R synapse. The observed STP of the selector is strongly influenced by the bottom metal–oxide interface, in which Ar plasma treatment on the bottom Pt electrode resulted in the annihilation of the STP feature in the selector. A mechanism is thus proposed to explain the observed STP, using the local electric field enhancement induced at the metal–oxide interface coupled with the drift-diffusion model of mobile O2– and Ti3+ ions. This work therefore provides a reliable means of producing the STP feature in a 1S1R device, which demonstrates the TIP capability sought after in hardware-based ANN.

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“…A common type of unit RRAM cell is 1T1R, i.e., one‐transistor and one‐resistor, where the transistor serves as an active selector for random access. [ 25,26 ] Passive unit RRAM cells are also considered, e.g., 1S1R (one‐passive selector and one‐resistor) [ 27,28 ] and 1 R (one self‐rectifying resistor). [ 18,29,30 ] For simplicity, we illustrate RRAM arrays as arrays of passive resistors hereafter.…”

Section: Preliminariesmentioning

confidence: 99%

Optimal Weight‐Splitting in Resistive Random Access Memory‐Based Computing‐in‐Memory Macros

Song

Kim

Jeong

2022

Advanced Intelligent Systems

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Deep learning (DL) prevalently applies to many tasks that are used to be done using a set of instructions. The improvement of DL capability is desired, which requires the deep neural network (DNN) to be deeper and larger. The wide use of DL with deep and large DNNs causes an immense workload for hardware, which is expected to continue onward. To support this trend, new hardware that accelerates major DL operations with reduced power consumption is strongly demanded. The current mainstream hardware for DL is general-purpose graphics processing units (GPGPUs), which enable parallel multiply-accumulate (MAC) operations-a major operational workload-but consume enormous power. DL accelerators aim to achieve high performance and power efficiency beyond GPGPUs.Several DL accelerators (popularly, referred to as neural processing units) have already been commercialized. [1,2] A nextgeneration (but not far) DL acceleration is considered to be based on the memory-centric architecture that minimizes data movement by computing data near or in memory domains, which is known to consume an immense amount of power. [3] Near-data processing (NDP) realizes parallel floating-point MAC operations in the vicinity of the memory domain, minimizing data movement. [4,5] However, this architecture also suffers from the notorious memory wall issue [6] due to large latency in access to random access memory (RAM). Additionally, NDP leverages its advantages only for memory-bound models, e.g., fully connected networks and recurrent neural networks, where one weight is used for one operation, unlike convolutional neural networks in which one weight is used for many operations.A workaround solution is to merge processing and memory domains into a single domain in which parallel MAC operations are executed in an analog manner. [7][8][9][10][11][12][13][14][15][16][17][18] This strategy realizes inplace MAC operations that allow memory access and operations to occur simultaneously in the same domain. We refer to this strategy as analog computing-in-memory (aCIM). Its feasibility has been demonstrated with various types of memory such as volatile memory, e.g., dynamic RAM, [7] static RAM, [8][9][10] and nonvolatile memory, e.g., magnetic RAM, [11] resistive RAM (RRAM). [12,13,[15][16][17] Among various embedded memories for aCIM, resistance-based nonvolatile RAMs have been attracting large attention because of their feasible analog MAC operations in parallel based on Kirchhoff 's current law (KCL). Particularly, RRAM offers multilevel data representations, so that a single RRAM cell can represent a multi-bit weight, which allows parallel fixed-point MAC operations at reduced space and computational complexities. However, the larger the parallelism and the number of levels of a single cell, the more likely a higher bit-resolution is required for the analog-to-digital converters (ADCs) to avoid data loss, which causes prohibitive power consumption and area overhead.In this regard, it may be necessary to limit the number of levels of a single cell and ...

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Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration

Cited by 14 publications

References 33 publications

Dot‐Product Operation in Crossbar Array Using a Self‐Rectifying Resistive Device

Dot‐Product Operation in Crossbar Array Using a Self‐Rectifying Resistive Device

Frequency-Dependent Synapse Weight Tuning in 1S1R with a Short-Term Plasticity TiO_x-Based Exponential Selector

Optimal Weight‐Splitting in Resistive Random Access Memory‐Based Computing‐in‐Memory Macros

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Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration

Cited by 14 publications

References 33 publications

Dot‐Product Operation in Crossbar Array Using a Self‐Rectifying Resistive Device

Dot‐Product Operation in Crossbar Array Using a Self‐Rectifying Resistive Device

Frequency-Dependent Synapse Weight Tuning in 1S1R with a Short-Term Plasticity TiOx-Based Exponential Selector

Optimal Weight‐Splitting in Resistive Random Access Memory‐Based Computing‐in‐Memory Macros

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Frequency-Dependent Synapse Weight Tuning in 1S1R with a Short-Term Plasticity TiO_x-Based Exponential Selector