2016
DOI: 10.1117/12.2218937
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Enhacement of intrafield overlay using a design based metrology system

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Cited by 2 publications
(5 citation statements)
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“…Similar to Scenario 1, both the inverse and forward models were built at three wavelengths. For Model 1 (Model 2), the inverse model achieved good approximation ability when the number of hidden layer neurons was greater than 21 (8), 6 (10), and 10 (8) at 200 nm, 400 nm, and 600 nm, respectively. Then, the forward model was constructed and applied.…”
Section: Results and Discussion For Scenario 2 531 Validation Of The ...mentioning
confidence: 99%
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“…Similar to Scenario 1, both the inverse and forward models were built at three wavelengths. For Model 1 (Model 2), the inverse model achieved good approximation ability when the number of hidden layer neurons was greater than 21 (8), 6 (10), and 10 (8) at 200 nm, 400 nm, and 600 nm, respectively. Then, the forward model was constructed and applied.…”
Section: Results and Discussion For Scenario 2 531 Validation Of The ...mentioning
confidence: 99%
“…For example, the etching and chemical mechanical polish process leads to geometric features such as the sidewall angle (SWA), top rounded angle, and the top angle, as illustrated in figures 1(b)-(d). Both two processes can lead to inaccurate measurement signals and ultimately unacceptable OVL metrology errors [8][9][10][11]. Therefore, it is necessary and critical to investigate the impacts of the target defects on the DBO metrology performance, particularly the metrology accuracy.…”
Section: Introductionmentioning
confidence: 99%
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“…One of the most important issues for improving the fabrication yield of semiconductor devices is to control layer-tolayer overlay, which makes it necessary to measure the overlay of the actual circuit pattern accurately. Due to design rule shrinkage of semiconductor devices, an optical-based measurement method for a dedicated overlay mark is no longer able to represent the exact circuit-level overlay [1]. The overlay of actual circuit patterns therefore needs to be measured by using a critical dimension scanning electron microscope (CD-SEM) [1,2].…”
Section: Introductionmentioning
confidence: 99%
“…Due to design rule shrinkage of semiconductor devices, an optical-based measurement method for a dedicated overlay mark is no longer able to represent the exact circuit-level overlay [1]. The overlay of actual circuit patterns therefore needs to be measured by using a critical dimension scanning electron microscope (CD-SEM) [1,2]. In cases where the actual circuit patterns of a measurement target consist of upper layer patterns and buried lower layer patterns, an overlay measurement method using both secondary electrons (SE) images and backscattered electrons (BSE) images obtained from a high voltage CD-SEM (HV-SEM) has been proposed [3].…”
Section: Introductionmentioning
confidence: 99%