Enhanced chip/package design for the IBM ES/9000

Belanger, R.; Conrady, D.P.; Honsinger, P. S.; Lavery, T.J.; Rothman, S. J.; Schanzenback, E.C.; Sitaram, Dinkar; Selinger, C.R.; DuBois, R.E.; Mahoney, G.; Miceli, Giacomo

doi:10.1109/iccd.1991.139969

Cited by 4 publications

(2 citation statements)

References 8 publications

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“…For placing chips on modules, an interactive graphic tool has been developed that supports manual placement of over 130 chips on multichip modules and also places modules on boards [83]. An integrated set of analysis tools was used to guide the manual placement.…”

Section: ) Placementmentioning

confidence: 99%

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EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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Section: ) Placementmentioning

confidence: 99%

“…With this complex circuit layouts began blocking more of the wiring space. A new wiring technique was invented to handle this [83]. The global router focused on congestion, capacitance, voltage drop, and min/max timing constraints, so the detailed router could focus on pin access.…”

Section: ) Placementmentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Hathaway

Habra

Schanzenbach

et al. 1997

The Journal of VLSI Signal Processing

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Net ordering for timing and wiring optimization

Selinger

Schell

Kleinman

Sixth Annual IEEE International ASIC Conference and Exhibit

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This paper discusses a methodology which allows a .package designer to totally optimize his package based on timing and wiring requirements, within one integrated tool. If all nets are optimized for timing, both critical and non-critical, then the package is not optimized from a wirability point of view. If all nets are optimized for wirability, then the package is not optimized from a timing perspective. If timing critical nets are optimized for timing and non-timing critical nets are optimized for wirability, then we have an optimized system. This paper discusses how the use of innovative net typing and pin ordering techniques allows for the maximum optimization of package hardware designs. The paper will further discuss a new approach to automatically apply the same net typing and pin ordering techniques to nets which violate all legal wiring rules and thus can not be mapped to a wiring rule solution through conventional means.

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Enhanced chip/package design for the IBM ES/9000

Cited by 4 publications

References 8 publications

EDA in IBM: past, present, and future

EDA in IBM: past, present, and future

Untitled

Net ordering for timing and wiring optimization

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