Enhanced Critical Electrical Characteristics in a Nanoscale Low-Voltage SOI MOSFET With Dual Tunnel Diode

Abstract

This brief presents a nanoscale low-voltage partially depleted silicon-on-insulator (SOI) structure with improved electrical performance. The brain of the proposed structure is a dual tunnel diode (DTD) composed of a heavily doped p-type L-shaped trench. The accumulated holes are effectively released by the tunnel current of DTD, thus reducing the critical kink effect. Compared with a conventional SOI, the proposed structure is considered as an efficient rival in nanoscaleintegrated applications. Index Terms-Dual tunnel diode (DTD), floating body effect (FBE), kink effect, L-shaped trench, partially depleted silicon-on-insulator MOSFET (PD-SOI MOSFET).

Drain current model for a hetero‐dielectric single gate tunnel field effect transistor (HDSG TFET)

“…Because of such stringent demands, the scaling of MOSFET will soon reach to its fundamental limits. Over the last few decades, researchers have paid their attention to propose alternative advanced transistor architecture and material 1,2 which can scale down the transistor below sub‐20‐nm gate length regime. Among the many possible candidates, junctionless field effect transistor (JLFET) is most promising devices due to their inherent ability of suppressing short channel effects (SCEs) 3,4 .…”

A Proposal of Vertical MOSFET and Electrothermal Analysis for Monolithic 3-D ICs

“…The transistors in M3D are implemented with SOI technology, which could effectively reduce the parasitic capacitance, leakage current, and power consumption [14][15][16]. While, the reported research on SOI transistors mainly focused on planar devices [17][18][19], there has rarely been any reports on SOI-based vertical MOSFET; the motivation for our present research. On the other hand, it is worth noting that thermal issues are critical in M3D ICs due to the stacking of power devices, and high temperatures can cause the degradation of device performance [20].…”

Temperature Dependent Characteristics and Electrostatic Threshold Voltage Tuning of Accumulated Body MOSFETs

“…Since the charges controlling the barrier height in MOSFETs are electrically isolated from the channel, there is no need for continuous charge injection from the control terminal, unlike BJTs. Ultra-thin-body silicon on insulator (SOI) [1]- [5], FinFET [6]- [9], tri-gate [10]- [15], gate-all-around [16]- [23] and multi-gate [24], [25] structures provide significant improvements in electrostatic control of the source-barrier in MOSFETs and suppress or eliminate the interface leakage currents [26]. Thin-body SOI and gate-all-around devices suffer from floating body effects [27], [28], where majority carriers trapped in the active region reduce the source-barrier (similar to charging of the base in BJTs) and cause soft errors.…”