2018
DOI: 10.1364/ome.9.000203
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Enhanced electro-optic performance of surface-treated nanowires: origin and mechanism of nanoscale current injection for reliable ultraviolet light-emitting diodes

Abstract: Self-assembled nanowires are posed to be viable alternatives to conventional planar structures, including the nitride epitaxy for optoelectronic, electronic and nano-energy applications. In many cases, current injection and extraction at the nanoscopic scale are essential for marked improvement at the macroscopic scale. In this investigation, we study the mechanism of nanoscale current injection and the origin of improvement of the flow of charged carriers at the group-III nitride semiconductor surface and met… Show more

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Cited by 12 publications
(11 citation statements)
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“…[25][26][27] The wide depletion layer region caused by Fermi level pinning results in a reduction in the free electron density near the semiconductor nanowire surfaces, thereby increasing the non-radiative recombination in the active regions and adversely affecting its quantum efficiency. 3,28 As confirmation, we observed a maximum J value of about 100 A/cm 2 at V F = 11 V at room temperature from the J-V F measurements on the parylene-free LED sample (compared to 140 A/cm 2 in the planarized sample, as reported earlier). Parylene-C is known to significantly suppress UV emission below 280 nm.…”
Section: Discussionsupporting
confidence: 88%
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“…[25][26][27] The wide depletion layer region caused by Fermi level pinning results in a reduction in the free electron density near the semiconductor nanowire surfaces, thereby increasing the non-radiative recombination in the active regions and adversely affecting its quantum efficiency. 3,28 As confirmation, we observed a maximum J value of about 100 A/cm 2 at V F = 11 V at room temperature from the J-V F measurements on the parylene-free LED sample (compared to 140 A/cm 2 in the planarized sample, as reported earlier). Parylene-C is known to significantly suppress UV emission below 280 nm.…”
Section: Discussionsupporting
confidence: 88%
“…In recent years, the heterogeneous integration of a variety of inorganic materials for fabricating electronic and optoelectronic devices on sapphire 1, 2 and silicon (Si) [3][4][5][6][7][8] has shown clear promise in reshaping the future of the electronics industry. Additionally, the high thermal and chemical stability of the group III-nitride material system indicates its potential application in harsh environments in comparison to conventional silicon-based optoelectronic devices, which have limited operating temperature range and require extra protective packaging.…”
Section: Introductionmentioning
confidence: 99%
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“…Most notably, the current signal vacancy area moves to the left pyramid facet, which in turn proves that the electrical response almost disappears at the descending pyramid facet with respect to the scan direction. Obviously, the effective nanocontact between the NWs and probe tips for either electrical conduction or deformation interaction has a strong correlation with their relative geometry under both motional and static conditions. , For better illustration, the 2D height and current distribution images are also presented in Figure S4.…”
Section: Discussionmentioning
confidence: 99%
“…By growing quasi-one-dimensional (quasi-1D) group III-nitride nanostructures using plasma-assisted molecular beam epitaxy (PA-MBE) [30,138,[213][214][215][216] , dislocation-and piezoelectric polarization-free Al x Ga 1−x N-based light-emitting nanowire structures can be realized. Nanowires have the advantage of allowing for the growth of lattice-mismatched foreign substrates, such as silicon and sapphire [217][218][219][220][221] , in addition to achieving nearly defect-free crystals [222,223] , and therefore, opportunity for fabricating high efficiency optoelectronic devices, including LEDs and lasers, because of the highly effective lateral stress relaxation associated with the nanowire large surface-area-to-volume ratios [224][225][226][227][228] . However, because of the higher surface-area-to-volume ratios in lower-dimen sional semiconductor structures and the subsequent formation of deep-level surface trap energy states, the intrinsic properties of d-dimensional semiconductor structures for all d {0,1,2} are directly influenced by their surface condition [229][230][231][232][233][234] .…”
mentioning
confidence: 99%