Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

Singh, H.; Agarwal, Kanak; Sylvester, Dennis; Nowka, K.

doi:10.1109/tvlsi.2007.904101

Cited by 91 publications

(49 citation statements)

References 13 publications

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“…The intermediate strength power gating was proposed in [27] to achieve the trade-off between suppression of leakage current and shorter wake-up time. To test this type of power-switching structures, a signature analysis technique was proposed in [28].…”

Section: Power Switchesmentioning

confidence: 99%

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Lin

2011

JLPEA

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Section: Power Switchesmentioning

confidence: 99%

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Lin

2011

JLPEA

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“…When the mode of operation changes from idle to active, the circuit requires a specific amount of time to charge the virtual power node or discharge the virtual ground node. This required time is referred to as wake up latency [20]. Several clock cycles are typically required for the virtual ground or power to stabilize.…”

Section: Previous Workmentioning

confidence: 99%

Path Specific Register Design to Reduce Standby Power Consumption

Salman

2011

JLPEA

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A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed register is used as a launching register in a noncritical path, trading clock-to-Q delay for leakage current. Other timing constraints such as setup and hold times are maintained the same not to introduce any timing violations. Alternatively, the second and third registers, trade, respectively, setup time and hold time for leakage current while maintaining clock-to-Q delay constant. The effect of the proposed methodology on leakage current is investigated for four technology nodes. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current.

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“…In [13], wake-up time is calculated by the charge stored in the body capacitances (C body ) divided by the Ion of switch transistors:…”

Section: Area and Power Cost Of Switch Transistorsmentioning

confidence: 99%

Temporal and spatial idleness exploitation for optimal-grained leakage control

Vemuri

Jone

2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Runtime leakage control techniques, such as power gating (PG) and body biasing (BB), have been applied in a coarse-grained manner traditionally. In order to enable more aggressive leakage reduction, researchers are seeking ways to control leakage with finer granularity. Our research proposes two novel methods, namely circuit clustering for temporal and spatial idleness exploitation, to systematically reduce the granularity of leakage control and improve leakage reduction. Another strength of this paper is the quantitative study of leakage saving and control cost by leakage control with different granularity. With our quantitative study, designers can make the trade-off between leakage saving and control cost, and decide the optimum granularity for leakage control. A heuristic algorithm has been developed to automate the two circuit clustering methods and determine the optimum granularity for any given circuit. The analysis and experiments of this paper is mainly based on RBB. They are also applicable to PG by modifying the cost function.

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Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

Cited by 91 publications

References 13 publications

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Low Power Testing—What Can Commercial Design-for-Test Tools Provide?

Path Specific Register Design to Reduce Standby Power Consumption

Temporal and spatial idleness exploitation for optimal-grained leakage control

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