Enhanced Negative Bias Stress Degradation in Multigate Polycrystalline Silicon Thin-Film Transistors

Zhang, Dongli; Wang, Mingxiang; Wang, Huaisheng; Yang, Yi-Lin

doi:10.1109/ted.2017.2737489

Cited by 8 publications

(10 citation statements)

References 18 publications

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“…Then, a non-uniform distribution of holes in the channel could be observed. [20] The validity of the proposed explanation on the nonuniform distribution of holes in the active layer was further verified, where the lifetime of holes was varied. As shown in Figs.…”

Section: Resultsmentioning

confidence: 76%

“…[4] In addition to the electrical performance of the asfabricated poly-Si TFTs, degradation behavior and the corresponding degradation mechanisms under various kinds of bias stress should be well understood before the optimal design of poly-Si TFTs and TFT-based circuits. Stress conditions, such as positive gate bias stress, negative gate bias stress (NBS), and hot-carrier (HC) effect, could all result into degradation in TFTs' electrical characteristics, but the typical degradation phenomena obviously differ, exhibiting positive [5] and negative shift of the transfer curves [6][7][8] and decreased on-state current (I on ) with unaffected subthreshold characteristics, [9] respectively.…”

Section: Introductionmentioning

confidence: 99%

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Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

Zhang¹,

Wang²,

Wang³

2022

Chinese Phys. B

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In this paper, the negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel was investigated. Results showed that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.

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Section: Resultsmentioning

confidence: 76%

Section: Introductionmentioning

confidence: 99%

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

Zhang¹,

Wang²,

Wang³

2022

Chinese Phys. B

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“…The inset shows the relationship between voltage shift (Δ V TH ) and stress time ( t ). A stretched exponential model as shown in eq can be utilized to fit the Δ V TH : where Δ V TH0 is the Δ V TH at infinite time, τ is the carrier characteristic detrapping time, and β is the stretched exponential exponent. The Δ V TH as a function of stress time fitted the stretched exponential model, indicating that the dominant degradation mechanism is the charge trapping behavior at the TFT channel .…”

Section: Resultsmentioning

confidence: 99%

“…The inset shows the relationship between voltage shift (ΔV TH ) and stress time (t). A stretched exponential model as shown in eq 1 can be utilized to fit the ΔV TH : 42 i k j j j j j j i k j j j j j i k j j j y { z z z y…”

Section: ■ Results and Discussionmentioning

confidence: 99%

High-Performance and Radiation-Hardened Solution-Processed ZrLaO Gate Dielectrics for Large-Area Applications

Fang

Zhao

Mitrović

et al. 2021

ACS Appl. Mater. Interfaces

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Radiation hardness is important for electronics operating in harsh radiation environments such as outer space and nuclear energy industries. In this work, radiation-hardened solution-processed ZrLaO thin films are demonstrated. The radiation effects on solution-processed ZrLaO thin films and InO x /ZrLaO thin-film transistors (TFTs) were systemically investigated. The Zr0.9La0.1O y thin films demonstrated excellent radiation hardness with negligible roughness, composition, electrical property, and bias-stress stability degradation after radiation exposure. The metal-oxide-semiconductor capacitors (MOSCAPs) based on Zr0.9La0.1O y gate dielectrics exhibited an ultralow flat band-voltage (V FB) sensitivity of 0.11 mV/krad and 0.19 mV/krad under low dose and high dose gamma irradiation conditions, respectively. The low dose condition had a 103 krad (SiO2) total dose and a 0.12 rad/s low dose rate, whereas the high dose condition had a 580 krad total dose and a 278 rad/s high dose rate. Furthermore, InO x /Zr0.9La0.1O y thin-film transistors (TFTs) exhibited a large I on/I off of 2 × 106, a small subthreshold swing (SS) of 0.11 V/dec, a small interface trap density (D it) of 1 × 1012 cm–2, and a 0.16 V threshold shift (ΔV TH) under 3600 s positive bias-stress (PBS). InO x /Zr0.9La0.1O y TFT-based resistor-loaded inverters demonstrated complete swing behavior, a static output gain of 13.3 under 4 V V DD, and an ∼9% radiation-induced degradation. Through separate investigation of the radiation-induced degradation on the semiconductor layer and dielectric layer of TFTs, it was found that radiation exposure mainly generated oxygen vacancies (Vo) and increased electron concentration among gate oxide. Nevertheless, the radiation-induced TFT instability was mainly related to the semiconductor layer degradation, which could be possibly suppressed by back-channel passivation. The demonstrated results indicate that solution-processed ZrLaO is a high-potential candidate for large-area electronics and circuits applied in harsh radiation environments. In addition, the detailed investigation of radiation-induced degradation on solution-processed high-k dielectrics in this work provided clear inspiration for developing novel flexible rad-hard dielectrics.

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“…Under these circumstances, technology computer-aided design (TCAD) simulation is necessary to systematically study and explore the physical mechanisms underlying the dependence of the TFT performance on the UR offset. In addition to conventional single-gate poly-Si TFTs, dual-gate poly-Si TFTs have also been widely used in display technology [16,17]. Although the UR offset frequently occurs in poly-Si TFTs, the influence of the UR offset especially on the performance of dual-gate poly-Si TFTs is seldom studied in literature.…”

Section: Introductionmentioning

confidence: 99%

Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

Hsu¹,

Chen²

2019

Semicond. Sci. Technol.

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In this paper, electrical characteristics of dual-gate polycrystalline silicon (poly-Si) thin film transistors (TFTs) with different undoped region (UR) offsets are investigated. Performance degradation of the poly-Si TFT is dependent on the offset value, offset direction, and offset location. In addition, the degradation is also dependent on the applied drain bias. Significant performance deterioration is observed when the offset is larger than ±0.4 μm. Even an offset in an individual UR can cause the degradation. At a low drain bias of −0.1 V, the degradation is independent on the direction and the location of the offset. When the drain bias increases to −10 V, the performance degradation of the TFT with the positive UR offset significantly reduces. The physical mechanisms underlying the performance variation are studied by analyzing the energy band diagrams, carrier concentration distributions, and electric field distributions.

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Enhanced Negative Bias Stress Degradation in Multigate Polycrystalline Silicon Thin-Film Transistors

Cited by 8 publications

References 18 publications

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

High-Performance and Radiation-Hardened Solution-Processed ZrLaO Gate Dielectrics for Large-Area Applications

Drain bias and position dependent performance degradation of dual-gate poly-Si TFTs with undoped region offsets

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