Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

Narula, Vishal; Agarwal, M. K.

doi:10.1088/1361-6641/ab3cac

Cited by 24 publications

(13 citation statements)

References 36 publications

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“…Due to the reduced channel complexity doping technique and no requirement of annealing techniques, this device [5] has gained importance. The junctionless devices require a thin and narrow channel region to accomplish lesser leakage current [5][6][7][8][9][10][11][12][13][14][15]. This type of transistor unlike the other transistors is without junctions, and there is zero concentration gradient from source to channel to drain [5].…”

Section: Sce's In Substrate Regionmentioning

confidence: 99%

“…The introduction of rectangular core-shell architecture on double gate junctionless transistors (RCS-DGJLT) significantly reduces the lesser leakage current. In [14], the authors have introduced a p-type RCS-DGJLT in which a rectangular core is doped with donor impurites and sandwiched between rectangular shells which are doped with acceptor impurities. In our work presented in [77], the n-type RCS-DGJLT is introduced along with the study of optimization of rectangular core thickness for different shell thickness.…”

Section: Logic Gate Implementationmentioning

confidence: 99%

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A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with an introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The short channel effects (SCE’s) and fabrication challenges have provoked the researchers to think for some other technologies to enhance the market of semiconductor devices. To overcome these SCE’s, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc. have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE’s have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE’s. Although the research on various issues has been addressed by different authors but still there is an impediment in the commercialization of the same device. The different technology boosters have been incorporated into junctionless based devices to escalate the performance. The technology boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices are studied on incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET’s and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.

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Section: Sce's In Substrate Regionmentioning

confidence: 99%

Section: Logic Gate Implementationmentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

Self Cite

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“…There are lot of advanced structures have been studied in the literature that reduces the short channel effects. The dielectric pocked based structures [4], Heterostructures and Homostructures [5], Oxide engineering [6], Gate material engineering [7], rectangular core-shell based architecture [8][9][10], dielectric modulated Ge/Si interfaced label free nanowire BIOFET for biomolecule detection by varying the work function and doping optimization for sensitivity enhancement [25], novel dielectric modulated step-graded germanium source bio tube FET for label free biosensing application etc are studied to improve the performance of the device at small channel lengths, so that the same devices can be used for digital and analog based applications. The analytical model is also presented by the authors [26] for biosensing performance of novel dielectric modulated triple surrounding gate germanium source MOSFET with step graded channel.The life time of the MOSFET and performance of the device gets hampered due to injection of hot electrons into the oxide region.…”

Section: Introductionmentioning

confidence: 99%

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

Mehta,

Kumar Arya,

Sharma

2024

Eng. Res. Express

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The detailed performance analysis of Core Shell Gate All Around junctionless field effect transistor along with CMOS inverter as an application with quantum models is presented in this paper for the first time. To appreciate the performance of the device and the application even at smaller channel length, the comparison with classical models is also presented. The OFF current was calculated as 3.6810-16A on incorporating the quantum models. The subthreshold swing (SS) and Drain induced barrier lowering (DIBL) are found to be near ideal values. The SS and DIBL was calculated as 62.82mV/dec and 33.4mV/V. The DIBL was found to be lesser by 52.82% with quantum model than classical model. The performance obtained using quantum models are better than the classical models in terms of different parameters such as OFF current, ON current, SS, DIBL, threshold voltage, transconductance. Further, the performance of the CMOS inverter with quantum models by considering the n-type and p-type Core Shell Gate All Around junctionless field effect transistor is also presented . The OFF current of p-type and n-type was matched before designing the application. A sharp transfer characteristics of the CMOS inverter is obtained. The performance was also studied by calculating the drain current from each of p-type and n-type and found to be more than 110-7A and SNM (Static Noise Margin) was calculated as 267mV. The transient response of CMOS inverter exhibits the potential of CMOS inverter using the proposed device even at smaller channel lengths.

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“…It is expected that the junctionless transistor can be an advantageous candidate for the miniaturized conventional MOSFET. The proposed junctionless structure has similar doping profile in the source, channel and drain regions and due to the absence of any physical p-n junction in the device, the sensor can be scaled down to nanoscale regime [19,20]. The main difference between the proposed device in this paper and conventional junctionless transistor is the employment of conducting polymer instead of metal for the gate material.…”

Section: Introductionmentioning

confidence: 99%

Design and simulation of a gas sensitive junctionless FinFET based on conducting polymer as the gate material

Mehrdad

Ahangari

2022

Phys. Scr.

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In this study, we demonstrate a multi-gas sensing device utilizing junctionless Fin-shaped Field Effect Transistor (FinFET) with conducting polymer as the gate material. The higher gas response is explained based on workfunction modulation of the conducting polymer gate, Poly(p-phenylene), upon gas molecule absorption. By definition, threshold voltage and off-state current variation before and after gas absorption are considered as two different measures for assessing the responsivity and sensitivity of the sensor. Basically, the main focus of this paper is designing a low power device, in which the change in the electrical characteristics of the device under gas exposure can be detected even in the absence of the gate bias. The high sensitivity of the proposed FinFET device as a gas sensor is mainly attributed to the large surface area of the 3D structure. We optimize the gas-sensing properties by investigating impact of critical physical and structural design parameters on the responsivity and selectivity of the sensor. In addition, statistical analysis is carried out to calculate coefficient of variation (CV) measure, for assessing the change in the responsivity of the gas sensor based on variation of main design parameters. Our results provide a route to design a low power CMOS compatible gas sensor that has fast response with high distinguishing selectivity and can be scaled down to nanoscale regime.

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Enhanced performance of double gate junctionless field effect transistor by employing rectangular core–shell architecture

Cited by 24 publications

References 36 publications

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

Design and simulation of a gas sensitive junctionless FinFET based on conducting polymer as the gate material

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