This paper proposes a p-type double gate junctionless field effect transistor having opposite doping in the core with that of the silicon body referring to rectangular core-shell (RCS) architecture. The use of RCS has significantly reduced the gate induced drain leakage and therefore, obtaining improved performance parameters. It is observed that the parasitic BJT action gets diminished in RCS architecture due to enlargement of tunneling width at the channel/drain interface. Further, after validating our simulations with the experimental results of junctionless p-type FET we demonstrated that insertion of oppositely doped core in silicon body helps to achieve volume depletion in OFF state. The simulation results show that junctionless FET with RCS architecture exhibit lower OFF current, higher ON/OFF ratio, better drain induced barrier lowering (DIBL) and superior subthreshold slope (SS) at lesser channel lengths. The measured values of OFF current, ON current, ON/OFF ratio, DIBL and SS at channel length 20 nm for RCS architecture are −9.96×10 −15 A, −2.33×10 −5 A, 0.23×10 10 , 42.1 mV V −1 and 67.7 mV/decade respectively. Interestingly, we have found a correlation between RCS thickness and channel length. Finally, a complementary metal oxide semiconductor (CMOS) inverter with RCS architecture is also designed. The voltage transfer characteristics of RCS based CMOS has been significantly improved as compared to the conventional junctionless CMOS inverter.

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This paper describes different architectures of a rectangular core shell double gate junctionless field effect transistor (RCS-DGJLT). The device performance has been studied when the core has either the same or opposite type of doping to the shell. It is found that an RCS-DGJLT with an oppositely doped core without heavily doped source/drain (S/D) extension regions exhibits an OFF current of ~10 −14 A and an ON current of ~10 −5 A. In addition, an RCS-DGJLT with heavily doped S/D extension and different placements of dopant concentration in the shell and core region is explored, so that control of charge carriers in the device during the ON and OFF states can be achieved. Further, the ON current is enhanced by doping engineering in the shell and core region without significantly degrading the OFF current. The RCS-DGJLT with heavily doped S/D extension along with oppositely doped core exhibits an OFF current of ~10 −12 A and an ON current of ~10 −4 A. The performance parameters such as the OFF current, ON current, ON/OFF current ratio, subthreshold slope, threshold voltage and transconductance are calculated. The performance of the proposed RCS-DGJLT fused with doping engineering is compared with previously published results on a DGJLT integrated with technology boosters from the literature, and is found to have superior performance t o its counterparts.

A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate the performance. An RCS-DGJLT device is designed using a visual technology computer aided design tool and look up table-based Verilog-A model has been designed to carry out spice simulation of the circuit. Device simulation of RCS-DGJLT shows the extraordinary performance when compared to conventional DGJLT. The RCS-DGJLT exhibits an OFF current (Ioff ) ∼10−14 A, ON current (Ion ) ∼10−5 A, ON/OFF current ratio (Ion /Ioff ) ∼109, subthreshold slope ∼68.9 mV decade−1 and drain induced barrier lowering ∼52.6 mV V−1. Also, the AC response of RCS-DGJLT exhibits good performance like lower miller capacitances of order 10–16 F, maximum unity gain frequency of 138.8 GHz, transconductance generation efficiency of 40 V−1, and gain-bandwidth product of 25.4 GHz. The common source amplifier circuit using RCS-DGJLT provides the amplification up to 3.3 times which implies gain (Av ) to be 3.3. The low leakage power of 10.4 pW and average power of 31.2 µW of common source amplifier circuit based on RCS-DGJLT shows the greater potential of using the proposed device in analog applications. Also, the complete flow chart of the process used to design an analog circuit based on proposed RCS-DGJLT is discussed. The result shows the potential of using the RCS-DGJLT device in designing high-frequency applications.

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