Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

Narula, Vishal; Agarwal, M. K.

doi:10.1088/1361-6641/abaaed

Cited by 17 publications

(8 citation statements)

References 40 publications

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“…The charge plasma technique has been used to dope the source and drain regions by choosing the necessary work function. A common source amplifier is thus designed using the device in visual FAB software [99]. Using the look-up table, the transient analysis of the circuit is studied.…”

Section: Circuit Implementation Using Junctionless Based Transistormentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

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The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with an introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The short channel effects (SCE’s) and fabrication challenges have provoked the researchers to think for some other technologies to enhance the market of semiconductor devices. To overcome these SCE’s, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc. have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE’s have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE’s. Although the research on various issues has been addressed by different authors but still there is an impediment in the commercialization of the same device. The different technology boosters have been incorporated into junctionless based devices to escalate the performance. The technology boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices are studied on incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET’s and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.

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Section: Circuit Implementation Using Junctionless Based Transistormentioning

confidence: 99%

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

Self Cite

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“…The circuit level simulations are carried out using Verilog-A model 42 in the Cadence Virtuoso tool. 43 Moreover, the look up table based approach is adopted for circuit level simulations.…”

Section: Circuit Analysismentioning

confidence: 99%

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Kumari,

Sreenivasulu,

Ajayan

et al. 2023

ECS J. Solid State Sci. Technol.

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For the first time, a nanosheet field effect transistor (NS FET) performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly-doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the dual-k spacer offered good electrostatic performance and high switching ratio. Moreover, the analog/RF figures of merit are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. Further, circuit level analysis is carried out using the Cadence tool for mixed circuit applications. The crucial circuits for IC design such as inverter, ring oscillator and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures

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“…There are lot of advanced structures have been studied in the literature that reduces the short channel effects. The dielectric pocked based structures [4], Heterostructures and Homostructures [5], Oxide engineering [6], Gate material engineering [7], rectangular core-shell based architecture [8][9][10], dielectric modulated Ge/Si interfaced label free nanowire BIOFET for biomolecule detection by varying the work function and doping optimization for sensitivity enhancement [25], novel dielectric modulated step-graded germanium source bio tube FET for label free biosensing application etc are studied to improve the performance of the device at small channel lengths, so that the same devices can be used for digital and analog based applications. The analytical model is also presented by the authors [26] for biosensing performance of novel dielectric modulated triple surrounding gate germanium source MOSFET with step graded channel.The life time of the MOSFET and performance of the device gets hampered due to injection of hot electrons into the oxide region.…”

Section: Introductionmentioning

confidence: 99%

“…For n-type RCS-DGJLT, shell is doped with donor impurities and core is doped with acceptor impurities and vice a versa for p-type RCS-DGJLT. The author have also studied an analog application as common source amplifier using RCS-DGLT in [10]. The similar idea of oppositely doped core sandwiched between the shells is incorporated in the Gate All Around based architecture in our previous work [14].…”

Section: Introductionmentioning

confidence: 99%

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

Mehta,

Kumar Arya,

Sharma

2024

Eng. Res. Express

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The detailed performance analysis of Core Shell Gate All Around junctionless field effect transistor along with CMOS inverter as an application with quantum models is presented in this paper for the first time. To appreciate the performance of the device and the application even at smaller channel length, the comparison with classical models is also presented. The OFF current was calculated as 3.6810-16A on incorporating the quantum models. The subthreshold swing (SS) and Drain induced barrier lowering (DIBL) are found to be near ideal values. The SS and DIBL was calculated as 62.82mV/dec and 33.4mV/V. The DIBL was found to be lesser by 52.82% with quantum model than classical model. The performance obtained using quantum models are better than the classical models in terms of different parameters such as OFF current, ON current, SS, DIBL, threshold voltage, transconductance. Further, the performance of the CMOS inverter with quantum models by considering the n-type and p-type Core Shell Gate All Around junctionless field effect transistor is also presented . The OFF current of p-type and n-type was matched before designing the application. A sharp transfer characteristics of the CMOS inverter is obtained. The performance was also studied by calculating the drain current from each of p-type and n-type and found to be more than 110-7A and SNM (Static Noise Margin) was calculated as 267mV. The transient response of CMOS inverter exhibits the potential of CMOS inverter using the proposed device even at smaller channel lengths.

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Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

Cited by 17 publications

References 40 publications

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

Quantum and classical simulation of core shell based junctionless field effect transistor with digital application

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