Investigating short channel effects and performance parameters of double gate junctionless transistor at various technology nodes

Narula, Vishal; Narula, Charu; Singh, Jatinder

doi:10.1109/raecs.2015.7453429

Cited by 15 publications

(6 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The bulk conduction takes place in junctionless transistors unlike surface conduction in conventional MOSFET. Figures 3(a), (b) shows the channel formation of junctionless and conventional MOSFET [16,17]. The work function difference between the gate and semiconductor is highly accountable for switching off the device.…”

Section: Image Sensorsmentioning

confidence: 99%

“…Once the gate voltage reaches the threshold value, a filament-type structure forms amid the source and drain as a channel. The volume of the channel keeps on increasing with the gate voltage until depletion regions get away and the device comes in flat band condition with maximum carriers in the channel [6,16,17]. Table 1 shows the general comparison between junctionless and conventional MOSFET.…”

Section: Image Sensorsmentioning

confidence: 99%

“…Different studies have been carried out in the literature to obtain better results by applying various ideas on the device structures such as high K dielectric materials [20][21][22], different semiconductor materials [23][24][25][26], high K spacers [27][28][29], mobility enhancement using strain technology [30][31][32][33]. Moreover, multi-gate junctionless transistors to improve gate control have also been studied [12,27,[34][35][36][37][38][39][40][41]. The study on the performance of device structures after the insertion of the dielectric pockets, ferroelectric as the gate material, thin gate dielectric, source and drain extension [42] etc has been presented in the literature.…”

Section: Image Sensorsmentioning

confidence: 99%

See 2 more Smart Citations

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

Self Cite

View full text Add to dashboard Cite

The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with an introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The short channel effects (SCE’s) and fabrication challenges have provoked the researchers to think for some other technologies to enhance the market of semiconductor devices. To overcome these SCE’s, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc. have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE’s have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE’s. Although the research on various issues has been addressed by different authors but still there is an impediment in the commercialization of the same device. The different technology boosters have been incorporated into junctionless based devices to escalate the performance. The technology boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices are studied on incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET’s and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.

show abstract

Section: Image Sensorsmentioning

confidence: 99%

Section: Image Sensorsmentioning

confidence: 99%

Section: Image Sensorsmentioning

confidence: 99%

See 1 more Smart Citation

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Narula,

Agarwal,

Verma

2024

Eng. Res. Express

Self Cite

View full text Add to dashboard Cite

show abstract

“…The source and drain junctions become close to each other on scaling the device such that the fabrication of such junctions becomes a laborious task. To overcome such pitfall, a device without source/drain junctions are introduced namely junctionless transistors (JLTs) [11][12][13][14][15][16][17]. The JLT basically consists of heavily uniform doped silicon film which has the same doping concentration from source to drain.…”

Section: Introductionmentioning

confidence: 99%

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

Narula

Agarwal

2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate the performance. An RCS-DGJLT device is designed using a visual technology computer aided design tool and look up table-based Verilog-A model has been designed to carry out spice simulation of the circuit. Device simulation of RCS-DGJLT shows the extraordinary performance when compared to conventional DGJLT. The RCS-DGJLT exhibits an OFF current (Ioff ) ∼10−14 A, ON current (Ion ) ∼10−5 A, ON/OFF current ratio (Ion /Ioff ) ∼109, subthreshold slope ∼68.9 mV decade−1 and drain induced barrier lowering ∼52.6 mV V−1. Also, the AC response of RCS-DGJLT exhibits good performance like lower miller capacitances of order 10–16 F, maximum unity gain frequency of 138.8 GHz, transconductance generation efficiency of 40 V−1, and gain-bandwidth product of 25.4 GHz. The common source amplifier circuit using RCS-DGJLT provides the amplification up to 3.3 times which implies gain (Av ) to be 3.3. The low leakage power of 10.4 pW and average power of 31.2 µW of common source amplifier circuit based on RCS-DGJLT shows the greater potential of using the proposed device in analog applications. Also, the complete flow chart of the process used to design an analog circuit based on proposed RCS-DGJLT is discussed. The result shows the potential of using the RCS-DGJLT device in designing high-frequency applications.

show abstract

“…Due to work function difference between gate and semiconductor, the channel of the device gets depleted in OFF state [10]. The central part of the device endures lesser force from the gate and thus on increasing the gate voltage the bulk conduction starts in the device [16]. Also, high doping concentration is required to achieve good ON current.…”

Section: Introductionmentioning

confidence: 99%

Impact of core thickness and gate misalignment on rectangular core–shell based double gate junctionless field effect transistor

Narula

Agarwal

2020

Semicond. Sci. Technol.

View full text Add to dashboard Cite

A rectangular core is inserted in double gate junctionless transistor (DGJLT) which separates the top shell and bottom shell in the device called as rectangular core-shell double gate junctionless transistor (RCS-DGJLT). The core doping and core thickness are optimized to improve the performance of RCS-DGJLT. The core thickness is optimized for different shell thicknesses in the device which has not been explored yet in the literature. An interesting observation is found that the core thickness should be equal to the shell thickness for smaller shell thicknesses, whereas the thicker core is required for larger shell thicknesses. RCS-DGJLT has shown remarkable improvement than DGJLT. Further, the effect of gate misalignment on either side (source/drain) of the channel in RCS-DGJLT and DGJLT is studied and compared on the basis of device performance. The study of gate misalignment becomes essential due to the complications on achieving perfectly aligned gates during the fabrication of double gate device. An RCS-DGJLT is found to have better tolerance to gate misalignment than DGJLT. The best parametric values like OFF current is ∼10 -16 A, ON current is ∼10 -5 A, subthreshold slope is nearly 66.2 mV/decade, ON/OFF current ratio is ∼10 10 , drain induced barrier lowering is ∼42.1 mV V −1 and threshold voltage ∼0.56 V at perfectly aligned gate condition is obtained on keeping core and shell thickness at 3 nm each. As per the analysis, the gate misalignment up to 20% on either side of the channel does not impact the performance parameters much and hence reduces the stress of meeting the requirement of perfect gate alignment.

show abstract

Investigating short channel effects and performance parameters of double gate junctionless transistor at various technology nodes

Cited by 15 publications

References 7 publications

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

A pathway to improve short channel effects of junctionless based FET’s after incorporating technology boosters: a review

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

Impact of core thickness and gate misalignment on rectangular core–shell based double gate junctionless field effect transistor

Contact Info

Product

Resources

About