Enhanced Performance of Gate-First p-Channel Metal–Insulator–Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method

Abstract

We demonstrated the use of an in situ metal/high-k fabrication method for improving the performance of metal-insulatorsemiconductor field-effect transistors (MISFETs). Gate-first pMISFETs with polycrystalline silicon (poly-Si)/TiN/HfSiON stacks were fabricated by techniques based on low-damage physical vapor deposition, in which high-quality HfSiON dielectrics were formed by the interface reaction between an ultrathin metal-Hf layer (0.5 nm thick) and a SiO 2 underlayer, and TiN electrodes were continuously deposited on the gate dielectrics without exposure to air. Gate-first pMISFETs with high carrier mobility and a low threshold voltage (V th ) were realized by reducing the carbon impurity in the gate stacks and improving the V th stability against thermal treatment. As a result, we obtained superior current drivability (I on ¼ 350 mA/mm at I off ¼ 200 pA/mm), which corresponds to a 13% improvement over that of conventional chemical vapor deposition-based metal/high-k devices.

Dielectric and Interface Properties of TiO2/HfSiO/SiO2 Layered Structures Fabricated by in situ PVD Method

“…Furthermore, we improved this method by using an ultrahigh vacuum (UHV)-based cluster tool, which enabled us to fabricate HfSiO/SiO 2 dielectrics and TiN metal electrodes continuously without exposure to air (in-situ SPIR method). We demonstrated the advantages of this method, in which EOT was scaled by controlling additional SiO 2 growth and leakage current was reduced by eliminating electrical defects due to carbon impurities in the gate stacks (2,3). However, for future CMOS devices, the gate leakage current must be fully reduced in the sub-1-nm EOT region, and the dielectric constant of HfSiO does not meet requirements.…”