2007
DOI: 10.1063/1.2745221
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Enhanced performance of solution-processed regioregular poly(3-hexylthiophene) thin-film transistors using planar bottom-contact architecture

Abstract: The authors report on the solution-processed planar bottom-contact (pBC) organic thin-film transistors and contact effect on gate threshold voltage incorporating regioregular poly(3-hexylthiophene) active layer. By employing pBC configuration, the transistors on SiO2∕Si without surface modification show much higher mobility, lower threshold voltage, and narrower dispersion of threshold voltage when compared to the conventional bottom-contact counterparts. The high mobility and lower threshold voltage are attri… Show more

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Cited by 12 publications
(14 citation statements)
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“…The mixture was heated up to 70 o C and stirred for 7 h. The mixture was poured to 500 mL of diethyl ether and the precipitate was washed with diethyl ether several times. The final product (2) was gathered and dried in a vacuum oven for 24 h. Figure 1 shows reaction scheme for the preparation of fluorinated styrene monomer (1) and copolymer gate dielectric (2).…”
Section: Methodsmentioning
confidence: 99%
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“…The mixture was heated up to 70 o C and stirred for 7 h. The mixture was poured to 500 mL of diethyl ether and the precipitate was washed with diethyl ether several times. The final product (2) was gathered and dried in a vacuum oven for 24 h. Figure 1 shows reaction scheme for the preparation of fluorinated styrene monomer (1) and copolymer gate dielectric (2).…”
Section: Methodsmentioning
confidence: 99%
“…Indium tin oxide (ITO) on a glass substrate was patterned by a conventional lithographic method for a Figure 1. The reaction scheme for the preparation of fluorinated styrene monomer (1) and copolymer gate dielectric, fluorinated styrene-alt-maleic anhydride copolymer (2). The copolymer (2) was prepared by a solution copolymerization.…”
Section: Methodsmentioning
confidence: 99%
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“…However, fabrication of embedded electrodes with planarity and flatness at the molecular scale is very challenging. In several studies, Xu et al 10,11 created embedded electrodes by first etching a silicon oxide substrate patterned by UV lithography followed by the evaporation of a layer of gold with a thickness equal to the etched material. However, the authors observed that the etch process produced trenches between the electrode and the dielectric.…”
Section: Introductionmentioning
confidence: 99%
“…This result can be explained by the increased contact resistance of the bottomcontact TFTs due to different semiconductor film crystallization/growth on the contact versus dielectric surface generating grain boundaries [14] as well as differences in electrode charge injection area between the two structures. [15] In addition, the transfer plots are independent on the gate bias scan rate, indicating minimal bias stress. Finally, atomic force microscopy (AFM, Fig.…”
mentioning
confidence: 99%