Enhanced performance of strained Strained-Si MOSFETs on CMP sige virtual substrate

Abstract

Strained-Si n-and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of -I .5 MV/cm. Improvements in current drive of 70% and 51% were also observed for n-and pMOSFETs (Lcm=0.24 pm), respectively. These results indicate that the planarization of the SiGe VS is a critical technology for developing high-performance strained-Si CMOS. IntroductionThe strained-Si MOSFET is promising as a device for sub-100-nm CMOS technology because of its high electron and hole mobilities. Developing this device currently requires a highquality SiGe virtual substrate (VS). Relaxation of strain during growth of the SiGe buffer layer always roughens the surface; hence, the surface quality of such substrates has, to date, been quite unsatisfactory. Previously reported increases in electron and hole mobility ( 1 -7) have been as high as 70% and 30%, respectively. In particular, the values for holes have been insufficient for fabricating high-performance CMOS. We have previously pointed out that surface roughness significantly affects mobility in strained-Si MOSFETs (6). In this paper, we demonstrate the great increases in both mobility and current drive that are obtained for both n-and p-MOS by employing CMP to produce a SiGe VS with a smooth surface.

High-performance nMOSFETs using a novel strained Si/SiGe CMOS architecture

“…The layer structure is additionally designed such that strain-compensation occurs between the n-and p-channels, and with strained channel thicknesses sufficient to allow conventional surface cleans and oxidation necessary for high-performance CMOS. The performance of the strained Si nMOSFETs presented in this paper exceeds that of recently reported devices [16] and is significantly enhanced compared with unstrained Si control devices over a wide range of gate lengths; our increases in drain current and transconductance are the highest reported to date. Furthermore, the performance gains are achieved without VS polishing thus the present technology is more compatible with conventional Si technology.…”

“…This is in spite of our devices having an increase in gate oxide thickness of 50% and characteristics measured without using an a.c. conductance technique to remove the effect of self-heating. At V and -V, of the strained Si device is approximately 0.55 mA m and is increased by over 140% compared with the Si control device, exceeding recently published data [14], [16], [31], [32]. Moreover, unlike the strained Si devices reported in [16] and [31], the excellent performance of our devices is achieved without requiring any CMP stages.…”

“…The self-heating of the strained Si/SiGe devices arises from the lower thermal conductivity of SiGe compared with Si [29] and results in a significantly elevated channel temperature [30]. Nevertheless, of the strained Si nMOSFETs is substantially higher than recently reported strained Si devices with a similar geometry and subthreshold characteristics [16]. This is in spite of our devices having an increase in gate oxide thickness of 50% and characteristics measured without using an a.c. conductance technique to remove the effect of self-heating.…”

“…C-V profiling of MOS capacitors on the Si/SiGe and Si control device wafers confirmed that of the Si/SiGe wafer was equivalent to that of the Si control wafers. Therefore, the lower values observed for the strained Si/SiGe device are mainly attributed to the differing electron affinities of the materials [16], [28]. The variation of transconductance with gate overdrive, -, for 0.2 m L 5 m W silicided strained Si and Si control devices is presented in Fig.…”

Electron transport in Si/SiGe modulation-doped heterostructures using Monte Carlo simulation

“…The strain-induced enhancement of carrier transport properties is also shown to improve significantly the current in P-channel and N-channel metal-oxide-semiconductor FETs (MOSFETs) designed for CMOS application [5][6].…”