Enhanced phase noise modeling of fractional-N frequency synthesizers

Abstract

Mathematical models for the behavior of fractional-N phase-locked-loop frequency synthesizers (Frac-N) are presented. The models are intended for calculating rms phase error and determining spurs in the output of Frac-N. The models describe noise contributions due to the charge pump (CP), the phase frequency detector (PFD), the loop filter, the voltage control osicllator, and the delta-sigma modulator. Models are presented for the effects of static CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. A simple analytic expression shows the level of 16 sequence noise caused by static CP current mismatch. We further show that un-equal rise time and fall time constants of the CP result in dynamic mismatch noise. Reset delay mismatch in PFD is shown to also contribute significantly to close-in phase noise. The model takes into account the reduction in CP thermal and flicker noise due to the changing duty cycle of Frac-N CP. Our model is therefore useful in characterizing the noise performance of Frac-N at the system-level, simplifying the design of fractional-N synthesizers and transmitters. Analytical and simulated results are compared and show good agreement with prior published data on Frac-N realizations.Index Terms-Charge pump (CP), delta-sigma, dynamic mismatch, dynamic mismatch corner frequency, flicker noise, flicker noise corner frequency, fractional-N frequency synthesizer (Frac-N), frequency synthesizer, gain mismatch, gain mismatch corner frequency, phase frequency detector (PFD), phase noise, reset delay mismatch, rms phase error, spurs, thermal noise, voltage-controlled oscillator (VCO).

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

“…This will improve the linearity of the phase detector (PD), which is composed of PFD and CP. As a result, noise generated by the SDM and folded down to small frequency offsets in the nonlinear PD is reduced, as described in [31,32,33,34,35]. Second, the PD linearity will be further improved by reducing turnon and turn-off time of CP1 in the fine tuning loop.…”

A tool for power and phase noise optimization in frequency synthesizers

“…2 in bold along with noise contributed from each individual component. We see that the out of band noise is dominated by the VCO and the in band noise is dominated by reference noise, divider noise, PFD, charge pump and etc., as is well known [18][19][20][21]. Additionally, the phase noise trades off with power differently in each block.…”

On the simulation of fast settling charge pump PLLs up to fourth order

“…It requires a linearization procedure or, equivalently, application of the impulse invariant transformation proposed in [9], which is based on approximating the CP current pulse with a weighted impulse. Similar approximations are introduced in the models developed for fractional-N frequency synthesizers in [10] and extended in [11]. The impulse invariant transformation has also been used to derive a design procedure to allow a settling time for the PLL in the order of a few reference periods [12].…”