Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm

Guerber, Jon; Venkatram, Hariprasath; Oh, Tae-Hwan; Moon, Un-Ku

doi:10.1109/iscas.2012.6271770

Cited by 19 publications

(12 citation statements)

References 8 publications

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“…7b between MCS and bit-skipping LSBFQ method at low activity inputs. Since MCS is known to be 87.5% more efficient than the conventional SAR switching [4], comparing the conven- tional switching would be even more favorable for the SSBQ. Using 10% of fullscale input to reflect low signal activity, there is a crossover point at around 0.01f s in which the SSBQ outperforms both the LSBFQ and the MCS SAR when SSB is set to 4.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Section IV provides simulation results showing the trade-off between switching energy and bitcycle range based on various bits set as the SSB. Furthermore, comparisons are made between the proposed solution, LSBFQ, and the most energy-efficient of the traditional MSB-first SAR methods, merged capacitor switching (MCS) [4]. Key contributions of this work are summarized in Section V.…”

Section: Introductionmentioning

confidence: 99%

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Selectable starting bit SAR ADC

Leung

Waters

Moon

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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Prior work used least-significant bit first quantization (LSBFQ) to conserve switching energy and comparator bitcycles, but is limited to low activity signals. Furthermore, LSBFQ results in a large bitcycle range in the quantizer. A novel selectable starting bit quantizer (SSBQ) is proposed which starts quantization with neither the MSB nor the LSB, but an intermediate bit chosen for target applications. It is shown that the proposed algorithm reduces bitcycle range in the quantizer compared to LSBFQ, and provides design flexibility for various activity signals. Furthermore, the proposed solution encompasses LSBFQ since it is a specific case of the proposed architecture. For target applications, the proposed solution will save bitcycles in an A/D conversion, as well as switching energy, over the LSBFQ and the merged capacitor switching (MCS) SAR, the most energyefficient traditional MSB-first SAR.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Selectable starting bit SAR ADC

Leung

Waters

Moon

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…The switched capacitors with charge redistribution architecture and opamp-less structure with digital control logics of SAR ADCs render them more adaptable to the technology and power supply scaling down, which enable them to achieve higher conversion speed and power efficiency. Numeric works have been done to improve the power efficiency and linearity of SAR ADCs, many of which [1,2,3,4,5,6,7,8,9,10,11] focus on switching methods of redistribution digital-to-analog converter (DAC) to reduce the power consumption.…”

Section: Introductionmentioning

confidence: 99%

“…These two switching procedures also have stable common-mode voltage which introduces less dynamic offset and error. Early reset merged capacitor switching (EMCS) method in [6] demonstrates 50% linearity improvement and 41.5% DAC power reduction compared to monotonic switching procedure, which is similar in binary-window structure [7]. Recently, several works [8,9,10,11] propose new switching methods with much less DAC power by adopting V cm ¼ V ref =2 as extra reference voltage.…”

Section: Introductionmentioning

confidence: 99%

Central span switching structure for SAR ADC with improved linearity and reduced DAC power

Gao

2015

IEICE Electron. Express

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Zero switching point effect for successive-approximation-register (SAR) analog-to-digital converters (ADCs) is analyzed in this paper. Central span switching procedures are presented based on shifting zero switching points of digital-to-analog converter (DAC) to improve the linearity of SAR ADC and reduce DAC energy. Several central span switching procedures modified from previous merged-capacitor-switching (MCS) and monotonic switching schemes are analyzed, which is central span MCS (CS-MCS) and central span monotonic (CS-MON). By splitting most-significantbit (MSB) capacitors, CS-MCS and CS-MON have linearity error reduction by a fact of 2 and ffiffi ffi 2 p . The DAC switching energy is reduced by 92.2% and 84.4% relative to conventional SAR ADC. With V cm applied as reference voltage at LSB conversion, the energy reduction can be increased to 96.1% and 92.17%. Moreover, with comparator input transistors split into two parts, the energy reduction of CS-MCS switching procedure can be 95.3% and 97.6% with V cm reference at LSB conversion. These central span switching procedures are not sensitive to V cm accuracy since it is the reference only at least-significant-bit (LSB) conversions.

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“…The V CM -based switching CDAC and the early reset merged switching CDAC use trireferences for the switching scheme and reduce the average switching energy by 87.5% and 89%, respectively, when compared with the conventional switching CDACs [10], [11]. In both of these CDACs, however, the energy saving comes at a price: multiple switches are required for each capacitor in the CDACs, which complicates the controlling logic and several capacitors must be reset using a well-prepared V CM reference, which requires an extra voltage buffer.…”

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confidence: 99%

A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme

Lin

Cheng

Tang

2016

IEEE Trans. VLSI Syst.

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This paper describes a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient trilevel alternate switching capacitive digital-to-analog converter (CDAC). The switching scheme of this CDAC preserves the features of the asymmetric-switching CDAC. By narrowing and smoothing the dynamic variation of DAC voltage, the switching scheme diminishes the dynamic offset effect induced by the asymmetric-switching CDAC. The CDAC reduces the capacitor requirement by almost fourfold and improves the average switching energy efficiency by almost 86.5% when compared with the conventional switching CDACs. This SAR ADC was implemented using the 90-nm CMOS technology, and its measured performances were as follows: 1) spurious free dynamic range of 56.98 dB; 2) signal-to-noiseand-distortion ratio of 68.79 dB; and 3) power dissipation of 3.45 µW at an operation of 0.5 V and 1.28 MS/s. The ADC achieves a figure-of-merit of 4.68-fJ/conversion-step.Index Terms-Analog-to-digital converter (ADC), capacitive digital-to-analog converter (CDAC), charge redistribution, dynamic offset, successive approximation register (SAR), trilevel switching.

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Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm

Cited by 19 publications

References 8 publications

Selectable starting bit SAR ADC

Selectable starting bit SAR ADC

Central span switching structure for SAR ADC with improved linearity and reduced DAC power

A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme

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