The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC) with quantization time information utilization is proposed. The TSAR examines the transient information of a typical dynamic SAR voltage comparator to provide accuracy, speed, and power benefits. Full half-bit redundancy is shown, allowing for residue shaping which provides an additional 6 dB of signal-to-quantization-noise ratio (SQNR). Synchronous quantizer speed enhancements allow for a shorter worst case conversion time. An increased monotonicity switching algorithm, stage skipping due to reference grouping, and SAR logic modifications minimize overall dynamic energy. The architecture has been shown to reduce capacitor array switching power consumption and digital-to-analog converter (DAC) driver power by about 60% in a mismatch limited SAR, reduce comparator activity by about 20%, and require only 8.03 average comparisons and 6.53 average DAC movements for a 10-b ADC output word. A prototype is fabricated in 0.13-m CMOS employing on-chip statistical time reference calibration, supply variability from 0.8 to 1.2 V, and small input signal power scaling. The chip consumes 84 W at 8 MHz with an effective number of bits of 9.3 for a figure of merit of 16.9 fJ/C-S for the 10-b prototype and 10.0 fJ/C-S for a 12-b enhanced prototype chip.Index Terms-Residue shaping, successive approximation analog-to-digital converter (SAR ADC), SAR ADC redundancy, SAR switching, ternary SAR (TSAR), time quantization.

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This paper proposes a blind calibration algorithm for suppressing nonlinearity in analog-to-digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the nonlinearity coefficients present in the system and can be operated to remove even and odd order nonlinearities simultaneously. The working of the algorithm is demonstrated on a first-order ring oscillator based ADC, whose performance is limited due to the nonlinearity present in its system. Built in 0.13 m CMOS, the algorithm improves the SNDR of the ADC by 39 dB, while improving SFDR by 45 dB.