Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/Si _x Ge_1–x–y Sn _y heterostructure model for low power FET applications

Abstract

High mobility materials are being studied to replace Si with the aim of enhancing the performance of nanoelectronic devices. Ge and III-V channels have recently received a lot of attention, where the combination of III-V channels in n-MOSFETs and Ge channels in p-MOSFETs integrated on Si substrates is regarded as a promising CMOS design. Ge integrated on Si is a very promising choice due to its superior transport properties and compatibility to CMOS technology. The main challenges faced by Ge-based FETs are the channel/gate interface quality, crystal defects due to integration on Si and the smaller bandgap compared to Si, which leads to elevated band-to-band-tunnelling leakage currents, setting limitations on the achievable off state current (I OFF ). In this work, we present results on the fabrication and characterization of vertical Ge-based p-channel planar doped barrier FET together with a simulation model based on extracted material data from our experimental work and literature. Based on the model, a design of a modified device using both planar doping and a heterostructure in the channel is presented. The channel engineered design uses a Ge/Si x Ge 1-x-y Sn y heterostructure, which is lattice matched to Ge, within the channel at different positions. The results show improved performance; the larger bandgap of the ternary alloy Si x Ge 1-x-y Sn y compared to Ge leads to a suppression of the I OFF as well as a reduced subthreshold swing, making the heterostructure device promising for energy efficient FET applications.

Performance and reliability assessment of source work function engineered charge plasma based Ti/HfO2/Al2O3/Ge, double gate TFET

“…Further, the reliability of Ti/HfO 2 /Al 2 O 3 /Ge CP-DGTFET was investigated with deviation in ITC from ±10 10 cm −2 to ±10 12 cm −2 . The ITCs are assumed to be uniformly distributed at the Al 2 O 3 /Ge interface based on experimental reports [42][43][44]. In addition, the effect of temperature variation on the Ti/HfO 2 /Al 2 O 3 /Ge CP-DGTFET device structure's performance was inspected in the presence of ±10 12 cm −2 ITCs.…”

Design of a triple pocket multi-gate material TFET structure for low-power applications

“…However, it suffers from a low ON state current (I ON ) and ambipolarity. Therefore, to improve the I ON of the device, TFET structures have been modified over the years [3][4][5][6][7][8][9][10], plus different kinds of materials have been used in the channel [11][12][13][14][15] and for gate formation [16]. Similarly for the device to exhibit a unipolar nature, several techniques have been proposed [17][18][19][20].…”