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In this study, the authors present a double-gate tunnel field-effect transistor with dual gate oxide thickness (henceforth referred to as DOT-DGTFET) to suppress ambipolar current conduction (I amb). Conventional n-type DGTFET conducts current for negative V GS also and poses a challenge for circuit design. Conduction current in n-type DGTFET for negative V GS is referred to as ambipolar current (I amb). In the proposed DOT-DGTFET structure, a thin gate oxide of 3 nm is used towards the source-channel junction and a thick gate oxide is used towards the drain-channel junction. Use of thicker gate oxide towards drain-channel junction suppresses I amb significantly while only marginally affecting I ON. Subsequently, the proposed technique for ambipolarity suppression is compared with some of the existing techniques and they observe that DOT-DGTFET suppresses ambipolarity significantly with minimal effect on the ON state current.

In this paper we propose a triple-pocket multi-gate material TFET (TP-TFET) device structure for a low-power and high-performance circuit design. The proposed device structure integrates the good features of both the conventional MOSFET and tunnel FET. This is achieved through three doped pockets and dual work-function gate material on near the source–channel junction. In the proposed device, the ON state conduction mechanism is dominated by an over-the-barrier thermal diffusion of carriers, thereby offering a high-value drive current. On the other hand, the subthreshold conduction mechanism is dominated by the tunnelling of carriers, thereby incurring a very small leakage current and offering a small subthreshold slope. We use 2D TCAD device simulations for the analysis of the TP-TFET and its comparison with the existing pocketed-heterogate TFET (PHG-TFET). We observe that the proposed TFET offers the average subthreshold slope (SSavg) of 2.85 mV dec−1 and ON current of ∼230 µA µm−1 as compared to the existing PHG-TFET, which offers SSavg of 44.91 mV dec−1 and I ON = ∼62 µA µm−1. Further, some benchmark circuits are implemented using these devices. A ring oscillator designed using the TP-TFET shows approximately a 6× higher frequency as compared to that designed using the PHG-TFET. The power delay product of the NAND gate and NOR gate obtained using these devices differ by approximately 3× to 20× as the supply voltage is decreased from 1.0 to 0.5 V.

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