Enhancement of underfill encapsulants for flip‐chip technology

Vincent, Michael; Wong, C.P.

doi:10.1108/09540919910293856

Cited by 17 publications

(7 citation statements)

References 14 publications

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“…In addition, studies [18], [19] suggested that the local viscosity variation in suspensions induced by shear migration (the particle motion across the streamlines by irreversible particle interactions) becomes negligible with the decrease of the filler particle size. In this paper, Underfill A has a mean diameter of 0.3 µm, much smaller than that of most previous underfill studies whose filler particles are several micrometers in diameter [1]- [4], [10]- [12], [17]- [19]. Fig.…”

Section: A Viscositymentioning

confidence: 97%

“…In order to redistribute the thermal stresses induced by the mismatch in the coefficient of thermal expansion among a silicon die, solder joints, and a substrate, underfill material is used to fill the gap containing thousands of bump interconnects between the die and substrate [1], [2]. The underfill material, a liquid encapsulant consisting of mostly epoxy resin and SiO 2 filler particles, is usually dispensed along a silicon die edge and flows through the multiply-connected gap region by capillary action.…”

Section: Introductionmentioning

confidence: 99%

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An Examination of Underfill Flow in Large Dies With Nonuniform Bump Patterns

Zheng

Sun

2010

IEEE Trans. Comp. Packag. Technol.

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In this paper, numerical modeling and experimental results are presented for underfill flow in a large die with a nonuniform bump pattern in a flip-chip packaging configuration. Two different 2-D flow models coupled with the volume-of-fluid method are applied to track the underfill flow front during the simulation of the flip-chip encapsulation process. The first model employs the modified Washburn model and uses a timedependent inlet velocity to account for the flow resistance across the gap direction in the presence of bump interconnects. The second model introduces a momentum source term in the Stokes equation to represent the gapwise flow resistance. Rheological properties, surface tension, and dynamic contact angles for commercial underfill material and the effect of flux residue on underfill wetting properties are experimentally determined. Simulation results based on the two models are compared with in-situ flow visualization conducted using bumped quartz dies. The modified Stokes model yields better predictions of the underfill penetration length as a function of time and the total flow-out time. This model is then used to investigate the effects of dynamic contact angles and temperature-dependent underfill viscosity on underfill flow in a large die with a nonuniform bump pattern.Index Terms-Flip-chip, nonuniform bump pattern, quartz die, simulation, underfill flow.

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Section: A Viscositymentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

An Examination of Underfill Flow in Large Dies With Nonuniform Bump Patterns

Zheng

Sun

2010

IEEE Trans. Comp. Packag. Technol.

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“…In the earlier days of flip chip technology, the chip was mounted onto the ceramic substrates and as the chip size was relatively small, the CTE mismatch between chip and substrate was not sufficient enough to cause reliability issue [4]. Since the late 1980s, the chip has been increasing in size to meet the growing demand on high performance of I/O.…”

Section: Introductionmentioning

confidence: 99%

“…Subsequently, the ceramic substrate was replaced by organic substrate because it is not able to adequately support the growing I/O counts due to its inherent limitation in thermal cycling reliability, density, and cost of use [5]. However, the use of organic substrate such as FR4 and polyimide has imposed significant thermal stresses on solder joints during thermal loading due to the greater difference in CTE between the chip and organic substrate [4,5]. Thus, the thermo-mechanical stress on solder joints became the cause of common failure of flip-chip package as the stress is induced to the interconnections repeatedly under cyclic thermal loading environment.…”

Section: Introductionmentioning

confidence: 99%

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Kwak

2014

J Mech Sci Technol

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Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermomechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captured deformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young's modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

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“…Since silicon nitride (Si 3 N 4 ) has the high dielectric constant, the complex insulated layer composed of Si 3 N 4 /benzocyclobutenone (BCBO) has a larger unit capacitance and smaller leakage current. [16][17][18][19][20][21][22][23][24] First, a film of 8 nm p-6P was deposited on the insulator, forming discontinuous islands when the substrate temperature was kept at 180 C, which is used to induce the growth of continuous polycrystalline rubrene thin films with large grains. Subsequently, the substrate temperature was dropped to 100 C, and the film of 20 nm rubrene was deposited on p-6P.…”

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confidence: 99%

High mobility organic thin-film transistors based on p-p heterojunction buffer layer

Qian

Wang

Yan

2013

Applied Physics Letters

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The p-p heterojunction of 5, 6, 11, 12-tetraphenylnaphthacene/vanadyl phthalocyanine, which has been used as the buffer layer, is demonstrated. The highest field-effect mobility is 5.1 cm2/Vs, which is one of the highest reported for polycrystalline rubrene thin film transistors. Current versus voltage characteristics of heterojunction diodes are utilized to investigate the charge injection mechanism, revealing the factors that bring about the improvement of carrier injection and the reduction of contact resistance. These results suggest that our approach is very promising to fabricate high performance organic thin-film transistors for practical applications in organic electronics.

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Enhancement of underfill encapsulants for flip‐chip technology

Cited by 17 publications

References 14 publications

An Examination of Underfill Flow in Large Dies With Nonuniform Bump Patterns

An Examination of Underfill Flow in Large Dies With Nonuniform Bump Patterns

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

High mobility organic thin-film transistors based on p-p heterojunction buffer layer

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