Enhancing bug hunting using high-level symbolic simulation

Chou, Hong-Zu; Lin, I.M.; Yang, Ching-Sung; Chang, Kuo–En; Kuo, Sy‐Yen

doi:10.1145/1531542.1531637

Cited by 6 publications

(4 citation statements)

References 13 publications

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“…The machine we used was a Dell PowerEdge 2900 (2GHz Xeon processor with 48 Gbytes of memory) running CentOS Linux 5.5. We implemented our algorithms on a commercial symbolic simulator [16] whose implementation detail can be found in [2], and the ABC package from University of California at Berkeley [18].…”

Section: Resultsmentioning

confidence: 99%

“…The runtime of all benchmarks was within 1 minute. Note that the number of patterns to trigger each bug can be considerably different from [2], [14] because we were measuring the number of patterns to trigger the bug, while [2], [14] measured the number to observe the bug at primary outputs. We also observed that several bugs could not be covered by random simulation using one million patterns, and it is difficult to distinguish the coverability of those bugs unless more patterns are simulated to a point where at least one pattern covers all the bugtriggering condition.…”

Section: A Covmet Accuracy Evaluationmentioning

confidence: 99%

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Improving design verifiability by early RTL coverability analysis

Chang

Jiang

et al. 2012

Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012)

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Achieving high coverage is an important goal in design verification. Fixing coverability problems found at the verification stage, however, can require tremendous effort. To address this problem, we propose a flow for analyzing code and variable-toggle coverability at the early-RTL block-level stage. In addition, we devise a novel technique to analyze the coverability problems so that engineers can resolve the issues more efficiently. By identifying coverability problems at early RTL design stages, design verifiability can be improved, thus reducing the effort required at the verification phase.

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Section: Resultsmentioning

confidence: 99%

Section: A Covmet Accuracy Evaluationmentioning

confidence: 99%

Improving design verifiability by early RTL coverability analysis

Chang

Jiang

et al. 2012

Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012)

Self Cite

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show abstract

“…Their approaches focus on how to handle RTL Verilog constructs containing delay and array structures in a BDD-based symbolic simulator. Since BDD can explode quickly, modern symbolic simulators use other logic representations and call backend solvers when necessary [5]. Sunkari et al.…”

Section: B Symbolic Simulationmentioning

confidence: 99%

Optimizing blocks in an SoC using symbolic code-statement reachability analysis

Chou¹,

Chang²,

Kuo³

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused design blocks. In this paper, we propose techniques and methodologies that utilize abundant external don't-cares that exist in an SoC environment for block optimization. Our symbolic codestatement reachability analysis can extract don't-care conditions from constrained-random testbenches or other design blocks to identify unreachable conditional blocks in the design code. Those blocks can then be removed before logic synthesis is performed to produce smaller and more power-efficient final circuits. Our results show that we can optimize designs under different constraints and provide additional flexibility for SoC design flows.

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“…Even though some classes of vulnerabilities reoccurring all the way through the software background exist for a long time, for example buffer overflows and format string vulnerabilities, automatically detecting their incarnations in specific software projects is often still not possible without significant expert knowledge [2]. The techniques that have been proposed include source code auditing, static program analysis, dynamic program analysis, and formal verification [3][4][5]. However, many of the methods lie on dangerous conclusions of the range concerning the costeffectiveness as represented in Figure 1.1.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Source Code Auditing using Fuzzy Decision Tree

Sahu¹,

Shrivastava²

2016

IJCA

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Here in this paper the discovery of Vulnerabilities in the Source Codes is proposed. The Proposed Methodology applied is based on the Concept of Fuzzy Based Decision Tree. The Methodology adopted here for the Checking of Codes Vulnerabilities provides efficient discovery of Vulnerabilities and hence provides improved performance and high precision and Recall. The Proposed Methodology Audits the source code and searches the possible vulnerabilities on the basis of Rules generated Fuzzy Decision Tree. Various Experimental results are achieved on numerous datasets and shows that the proposed methodology provides better accuracy in comparison.

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Enhancing bug hunting using high-level symbolic simulation

Cited by 6 publications

References 13 publications

Improving design verifiability by early RTL coverability analysis

Improving design verifiability by early RTL coverability analysis

Optimizing blocks in an SoC using symbolic code-statement reachability analysis

An Efficient Source Code Auditing using Fuzzy Decision Tree

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